[thirdparty/u-boot.git] / board / conclusive / kstr-sama5d27 / kstr-sama5d27.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * kstr-sama5d27.c - Board init file for Conclusive KSTR-SAMA5D27 board
 * Copyright (C) 2021-2023 Conclusive Engineering Sp. z o. o.
 */

#include <common.h>
#include <debug_uart.h>
#include <init.h>
#include <env.h>
#include <fdt_support.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_sdhci.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>
#include <linux/delay.h>

#ifdef CONFIG_USB_GADGET_ATMEL_USBA
#include <asm/arch/atmel_usba_udc.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void board_uart1_hw_init(void)
{
	/* URXD1 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);
	/* UTXD1 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);
	at91_periph_clk_enable(ATMEL_ID_UART1);
}

void board_debug_uart_init(void)
{
	board_uart1_hw_init();
}
#endif

void board_lan8720a_init(void)
{
	/* LAN8720A_nRST */
	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 0);
	/*
	 * Force 0 on RXER/PHYAD0. LAN8720A chipset will latch with address 0 on
	 * MDIO bus.
	 */
	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0);
	/* Minimal delay of reset signal is 25 ms */
	mdelay(30);
	/* LAN8720A_nRST */
	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
}

void board_usba_init(void)
{
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	/* USB device peripheral initialization: sama5d2_devices.c */
	at91_udp_hw_init();
	/* USB device controller drivers/usb/gadget/atmel_usba_udc.c */
	usba_udc_probe(&pdata);
#endif
}

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
	debug_uart_init();
#endif

	return 0;
}
#endif

int ft_board_setup(void *blob, struct bd_info *bd)
{
	char *wlanaddr = env_get("eth1addr");

	if (wlanaddr)
		do_fixup_by_compat(blob, "brcm,bcm4329-fmac", "local-mac-address",
				   wlanaddr, strlen(wlanaddr), 1);
	else
		printf("Not setting WIFI mac address. Check if EEPROM TLV is correctly set up.\n");

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

	board_usba_init();
	board_lan8720a_init();

	return 0;
}

static int settings_r(void)
{
	mac_read_from_eeprom();
	serial_read_from_eeprom(0);

	return 0;
}
EVENT_SPY_SIMPLE(EVT_SETTINGS_R, settings_r);

#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
int checkboard(void)
{
	const char *serial_number;

	serial_number = env_get("serial#");
	if (!serial_number)
		printf("Warning: unknown serial number.\n");
	else
		printf("S/N:   %s\n", serial_number);

	return 0;
}
#endif

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
	return 0;
}
#endif

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
				    CFG_SYS_SDRAM_SIZE);
	return 0;
}

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
}

static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
{
	ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);

	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_13 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
		    ATMEL_MPDDRC_CR_DIC_DS |
		    ATMEL_MPDDRC_CR_ZQ_LONG |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);

	ddrc->rtr = 0x511;

	ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
		      (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));

	ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
		      (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
		      (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));

	ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
		      (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
		      (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
}

void mem_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
	struct atmel_mpddrc_config ddrc_config;
	u32 reg;

	ddrc_conf(&ddrc_config);

	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	writel(AT91_PMC_DDR, &pmc->scer);

	reg = readl(&mpddrc->io_calibr);
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
	writel(reg, &mpddrc->io_calibr);

	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
	       &mpddrc->rd_data_path);

	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);

	writel(0x3, &mpddrc->cal_mr4);
	writel(64, &mpddrc->tim_cal);
}

void at91_pmc_init(void)
{
	u32 tmp;

	/*
	 * While coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz,
	 * so we need to slow down and configure MCKR accordingly.
	 * This is why we have a special flavor of the switching function.
	 */
	tmp = AT91_PMC_MCKR_PLLADIV_2 |
	      AT91_PMC_MCKR_MDIV_3 |
	      AT91_PMC_MCKR_CSS_MAIN;
	at91_mck_init_down(tmp);

	tmp = AT91_PMC_PLLAR_29 |
	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
	      AT91_PMC_PLLXR_MUL(40) |
	      AT91_PMC_PLLXR_DIV(1);
	at91_plla_init(tmp);

	tmp = AT91_PMC_MCKR_H32MXDIV |
	      AT91_PMC_MCKR_PLLADIV_2 |
	      AT91_PMC_MCKR_MDIV_3 |
	      AT91_PMC_MCKR_CSS_PLLA;
	at91_mck_init(tmp);
}
#endif
Commit	Line	Data
27347893 AR	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* kstr-sama5d27.c - Board init file for Conclusive KSTR-SAMA5D27 board
	4	* Copyright (C) 2021-2023 Conclusive Engineering Sp. z o. o.
	5	*/
	6
d678a59d	7	#include <common.h>
27347893 AR	8	#include <debug_uart.h>
	9	#include <init.h>
	10	#include <env.h>
	11	#include <fdt_support.h>
	12	#include <asm/global_data.h>
	13	#include <asm/io.h>
	14	#include <asm/arch/at91_common.h>
	15	#include <asm/arch/atmel_pio4.h>
	16	#include <asm/arch/atmel_mpddrc.h>
	17	#include <asm/arch/atmel_sdhci.h>
	18	#include <asm/arch/clk.h>
	19	#include <asm/arch/gpio.h>
	20	#include <asm/arch/sama5d2.h>
	21	#include <linux/delay.h>
	22
	23	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	24	#include <asm/arch/atmel_usba_udc.h>
	25	#endif
	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	#ifdef CONFIG_DEBUG_UART_BOARD_INIT
	30	static void board_uart1_hw_init(void)
	31	{
	32	/* URXD1 */
	33	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);
	34	/* UTXD1 */
	35	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);
	36	at91_periph_clk_enable(ATMEL_ID_UART1);
	37	}
	38
	39	void board_debug_uart_init(void)
	40	{
	41	board_uart1_hw_init();
	42	}
	43	#endif
	44
	45	void board_lan8720a_init(void)
	46	{
	47	/* LAN8720A_nRST */
	48	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 0);
	49	/*
	50	* Force 0 on RXER/PHYAD0. LAN8720A chipset will latch with address 0 on
	51	* MDIO bus.
	52	*/
	53	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0);
	54	/* Minimal delay of reset signal is 25 ms */
	55	mdelay(30);
	56	/* LAN8720A_nRST */
	57	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
	58	}
	59
	60	void board_usba_init(void)
	61	{
	62	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	63	/* USB device peripheral initialization: sama5d2_devices.c */
	64	at91_udp_hw_init();
	65	/* USB device controller drivers/usb/gadget/atmel_usba_udc.c */
	66	usba_udc_probe(&pdata);
	67	#endif
	68	}
	69
	70	#ifdef CONFIG_BOARD_EARLY_INIT_F
	71	int board_early_init_f(void)
72	{
73	#ifdef CONFIG_DEBUG_UART
74	debug_uart_init();
75	#endif
76
77	return 0;
78	}
79	#endif
80
81	int ft_board_setup(void blob, struct bd_info bd)
82	{
83	char *wlanaddr = env_get("eth1addr");
84
85	if (wlanaddr)
86	do_fixup_by_compat(blob, "brcm,bcm4329-fmac", "local-mac-address",
87	wlanaddr, strlen(wlanaddr), 1);
88	else
89	printf("Not setting WIFI mac address. Check if EEPROM TLV is correctly set up.\n");
90
91	return 0;
92	}
93
94	int board_init(void)
95	{
96	/* address of boot parameters */
97	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
98
99	board_usba_init();
100	board_lan8720a_init();
101
102	return 0;
103	}
104
105	static int settings_r(void)
106	{
107	mac_read_from_eeprom();
108	serial_read_from_eeprom(0);
109
110	return 0;
111	}
112	EVENT_SPY_SIMPLE(EVT_SETTINGS_R, settings_r);
113
114	#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
115	int checkboard(void)
116	{
117	const char *serial_number;
118
119	serial_number = env_get("serial#");
120	if (!serial_number)
121	printf("Warning: unknown serial number.\n");
122	else
123	printf("S/N: %s\n", serial_number);
124
125	return 0;
126	}
127	#endif
128
129	#ifdef CONFIG_MISC_INIT_R
130	int misc_init_r(void)
131	{
132	return 0;
133	}
134	#endif
135
136	int dram_init(void)
137	{
138	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
139	CFG_SYS_SDRAM_SIZE);
140	return 0;
141	}
142
143	/* SPL */
144	#ifdef CONFIG_SPL_BUILD
145	void spl_board_init(void)
146	{
147	}
148
149	static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
150	{
151	ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
152
153	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
154	ATMEL_MPDDRC_CR_NR_ROW_13 \|
155	ATMEL_MPDDRC_CR_CAS_DDR_CAS3 \|
156	ATMEL_MPDDRC_CR_DIC_DS \|
157	ATMEL_MPDDRC_CR_ZQ_LONG \|
158	ATMEL_MPDDRC_CR_NB_8BANKS \|
159	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
160	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
161
162	ddrc->rtr = 0x511;
163
164	ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) \|
165	(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) \|
166	(3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) \|
167	(9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) \|
168	(3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) \|
169	(4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) \|
170	(4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) \|
171	(2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
172
173	ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) \|
174	(23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) \|
175	(200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) \|
176	(3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
177
178	ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) \|
179	(8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) \|
180	(4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) \|
181	(4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) \|
182	(8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
183	}
184
185	void mem_init(void)
186	{
187	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
188	struct atmel_mpddr mpddrc = (struct atmel_mpddr )ATMEL_BASE_MPDDRC;
189	struct atmel_mpddrc_config ddrc_config;
190	u32 reg;
191
192	ddrc_conf(&ddrc_config);
193
194	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
195	writel(AT91_PMC_DDR, &pmc->scer);
196
197	reg = readl(&mpddrc->io_calibr);
198	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
199	reg \|= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
200	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
201	reg \|= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
202	writel(reg, &mpddrc->io_calibr);
203
204	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
205	&mpddrc->rd_data_path);
206
207	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
208
209	writel(0x3, &mpddrc->cal_mr4);
210	writel(64, &mpddrc->tim_cal);
211	}
212
213	void at91_pmc_init(void)
214	{
215	u32 tmp;
216
217	/*
218	* While coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz,
219	* so we need to slow down and configure MCKR accordingly.
220	* This is why we have a special flavor of the switching function.
221	*/
222	tmp = AT91_PMC_MCKR_PLLADIV_2 \|
223	AT91_PMC_MCKR_MDIV_3 \|
224	AT91_PMC_MCKR_CSS_MAIN;
225	at91_mck_init_down(tmp);
226
227	tmp = AT91_PMC_PLLAR_29 \|
228	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
229	AT91_PMC_PLLXR_MUL(40) \|
230	AT91_PMC_PLLXR_DIV(1);
231	at91_plla_init(tmp);
232
233	tmp = AT91_PMC_MCKR_H32MXDIV \|
234	AT91_PMC_MCKR_PLLADIV_2 \|
235	AT91_PMC_MCKR_MDIV_3 \|
236	AT91_PMC_MCKR_CSS_PLLA;
237	at91_mck_init(tmp);
238	}
239	#endif