[people/ms/u-boot.git] / board / cpu86 / cpu86.c

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "cpu86.h"

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf ppar psor pdir podr pdat */
	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
    },

    /* Port B configuration */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
    },

    /* Port C */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
    },

    /* Port D */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
#if defined(CONFIG_SOFT_I2C)
	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
#else
#if defined(CONFIG_HARD_I2C)
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
#else /* normal I/O port pins */
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
#endif
#endif
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
    }
};

/* ------------------------------------------------------------------------- */

/* Check Board Identity:
 */
int checkboard (void)
{
	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
	return 0;
}

/* ------------------------------------------------------------------------- */

/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 *
 * This routine performs standard 8260 initialization sequence
 * and calculates the available memory size. It may be called
 * several times to try different SDRAM configurations on both
 * 60x and local buses.
 */
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
			  ulong orx, volatile uchar * base)
{
	volatile uchar c = 0xff;
	volatile uint *sdmr_ptr;
	volatile uint *orx_ptr;
	ulong maxsize, size;
	int i;

	/* We must be able to test a location outsize the maximum legal size
	 * to find out THAT we are outside; but this address still has to be
	 * mapped by the controller. That means, that the initial mapping has
	 * to be (at least) twice as large as the maximum expected size.
	 */
	maxsize = (1 + (~orx | 0x7fff)) / 2;

	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
	 * we are configuring CS1 if base != 0
	 */
	sdmr_ptr = &memctl->memc_psdmr;
	orx_ptr = &memctl->memc_or2;

	*orx_ptr = orx;

	/*
	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	 *
	 * "At system reset, initialization software must set up the
	 *  programmable parameters in the memory controller banks registers
	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	 *  system software should execute the following initialization sequence
	 *  for each SDRAM device.
	 *
	 *  1. Issue a PRECHARGE-ALL-BANKS command
	 *  2. Issue eight CBR REFRESH commands
	 *  3. Issue a MODE-SET command to initialize the mode register
	 *
	 *  The initial commands are executed by setting P/LSDMR[OP] and
	 *  accessing the SDRAM with a single-byte transaction."
	 *
	 * The appropriate BRx/ORx registers have already been set when we
	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
	 */

	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
	*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
	for (i = 0; i < 8; i++)
		*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */

	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
	*base = c;

	size = get_ram_size((long *)base, maxsize);

	*orx_ptr = orx | ~(size - 1);

	return (size);
}

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;

#ifndef CONFIG_SYS_RAMBOOT
	ulong size8, size9;
#endif
	long psize;

	psize = 32 * 1024 * 1024;

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
	memctl->memc_psrt = CONFIG_SYS_PSRT;

#ifndef CONFIG_SYS_RAMBOOT
	/* 60x SDRAM setup:
	 */
	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
			  (uchar *) CONFIG_SYS_SDRAM_BASE);
	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
			  (uchar *) CONFIG_SYS_SDRAM_BASE);

	if (size8 < size9) {
		psize = size9;
		printf ("(60x:9COL) ");
	} else {
		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
				  (uchar *) CONFIG_SYS_SDRAM_BASE);
		printf ("(60x:8COL) ");
	}

#endif	/* CONFIG_SYS_RAMBOOT */

	icache_enable ();

	return (psize);
}

#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
Commit	Line	Data
f8cac651 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <ioports.h>
	26	#include <mpc8260.h>
	27	#include "cpu86.h"
	28
	29	/*
	30	* I/O Port configuration table
	31	*
	32	* if conf is 1, then that port pin will be configured at boot time
	33	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	34	*/
	35
	36	const iop_conf_t iop_conf_tab[4][32] = {
	37
	38	/* Port A configuration */
	39	{ /* conf ppar psor pdir podr pdat */
	40	/* PA31 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII COL */
	41	/* PA30 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII CRS */
	42	/* PA29 / { 1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_ER */
	43	/* PA28 / { 1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_EN */
	44	/* PA27 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_DV */
	45	/* PA26 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_ER */
	46	/* PA25 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII MDIO */
	47	/* PA24 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII MDC */
	48	/* PA23 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII MDIO */
	49	/* PA22 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII MDC */
	50	/* PA21 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[3] */
	51	/* PA20 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[2] */
	52	/* PA19 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[1] */
	53	/* PA18 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[0] */
	54	/* PA17 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[0] */
	55	/* PA16 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[1] */
	56	/* PA15 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[2] */
	57	/* PA14 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[3] */
	58	/* PA13 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII TXSL1 */
	59	/* PA12 / { 1, 0, 0, 1, 0, 1 }, / FCC2 MII TXSL0 */
	60	/* PA11 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII TXSL1 */
	61	/* PA10 / { 1, 0, 0, 1, 0, 1 }, / FCC1 MII TXSL0 */
	62	/* PA9 / { 0, 1, 0, 1, 0, 0 }, / SMC2 TXD */
	63	/* PA8 / { 0, 1, 0, 0, 0, 0 }, / SMC2 RXD */
	64	/* PA7 / { 0, 0, 0, 0, 0, 0 }, / PA7 */
65	/* PA6 / { 1, 0, 0, 1, 0, 1 }, / FCC2 MII PAUSE */
66	/* PA5 / { 1, 0, 0, 1, 0, 1 }, / FCC1 MII PAUSE */
67	/* PA4 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII PWRDN */
68	/* PA3 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII PWRDN */
69	/* PA2 / { 0, 0, 0, 0, 0, 0 }, / PA2 */
70	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FCC2 MII MDINT */
71	/* PA0 / { 1, 0, 0, 1, 0, 0 } / FCC1 MII MDINT */
72	},
73
74	/* Port B configuration */
75	{ /* conf ppar psor pdir podr pdat */
76	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
77	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
78	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
79	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
80	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
81	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
82	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
83	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
84	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
85	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
86	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
87	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
88	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
89	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
90	/* PB17 / { 0, 0, 0, 0, 0, 0 }, / PB17 */
91	/* PB16 / { 0, 0, 0, 0, 0, 0 }, / PB16 */
92	/* PB15 / { 0, 0, 0, 0, 0, 0 }, / PB15 */
93	/* PB14 / { 0, 0, 0, 0, 0, 0 }, / PB14 */
94	/* PB13 / { 0, 0, 0, 0, 0, 0 }, / PB13 */
95	/* PB12 / { 0, 0, 0, 0, 0, 0 }, / PB12 */
96	/* PB11 / { 0, 0, 0, 0, 0, 0 }, / PB11 */
97	/* PB10 / { 0, 0, 0, 0, 0, 0 }, / PB10 */
98	/* PB9 / { 0, 0, 0, 0, 0, 0 }, / PB9 */
99	/* PB8 / { 0, 0, 0, 0, 0, 0 }, / PB8 */
100	/* PB7 / { 0, 0, 0, 0, 0, 0 }, / PB7 */
101	/* PB6 / { 0, 0, 0, 0, 0, 0 }, / PB6 */
102	/* PB5 / { 0, 0, 0, 0, 0, 0 }, / PB5 */
103	/* PB4 / { 0, 0, 0, 0, 0, 0 }, / PB4 */
104	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / PB3 */
105	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / PB2 */
106	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / PB1 */
107	/* PB0 / { 0, 0, 0, 0, 0, 0 } / PB0 */
108	},
109
110	/* Port C */
111	{ /* conf ppar psor pdir podr pdat */
112	/* PC31 / { 0, 0, 0, 0, 0, 0 }, / PC31 */
113	/* PC30 / { 0, 0, 0, 0, 0, 0 }, / PC30 */
114	/* PC29 / { 1, 0, 0, 0, 0, 0 }, / SCC1 CTS */
115	/* PC28 / { 1, 0, 0, 0, 0, 0 }, / SCC2 CTS */
116	/* PC27 / { 0, 0, 0, 0, 0, 0 }, / PC27 */
117	/* PC26 / { 0, 0, 0, 0, 0, 0 }, / PC26 */
118	/* PC25 / { 0, 0, 0, 0, 0, 0 }, / PC25 */
119	/* PC24 / { 0, 0, 0, 0, 0, 0 }, / PC24 */
120	/* PC23 / { 0, 0, 0, 0, 0, 0 }, / FDC37C78 DACFD */
121	/* PC22 / { 0, 0, 0, 0, 0, 0 }, / FDC37C78 DNFD */
122	/* PC21 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RX_CLK */
123	/* PC20 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII TX_CLK */
124	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK */
125	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII TX_CLK */
126	/* PC17 / { 0, 0, 0, 0, 0, 0 }, / PC17 */
127	/* PC16 / { 0, 0, 0, 0, 0, 0 }, / PC16 */
128	/* PC15 / { 0, 0, 0, 0, 0, 0 }, / PC15 */
129	/* PC14 / { 0, 0, 0, 0, 0, 0 }, / PC14 */
130	/* PC13 / { 0, 0, 0, 0, 0, 0 }, / PC13 */
131	/* PC12 / { 0, 0, 0, 0, 0, 0 }, / PC12 */
132	/* PC11 / { 0, 0, 0, 0, 0, 0 }, / PC11 */
133	/* PC10 / { 0, 0, 0, 0, 0, 0 }, / PC10 */
134	/* PC9 / { 0, 0, 0, 0, 0, 0 }, / FC9 */
135	/* PC8 / { 0, 0, 0, 0, 0, 0 }, / PC8 */
136	/* PC7 / { 0, 0, 0, 0, 0, 0 }, / PC7 */
137	/* PC6 / { 0, 0, 0, 0, 0, 0 }, / PC6 */
138	/* PC5 / { 0, 0, 0, 0, 0, 0 }, / PC5 */
139	/* PC4 / { 0, 0, 0, 0, 0, 0 }, / PC4 */
140	/* PC3 / { 0, 0, 0, 0, 0, 0 }, / PC3 */
141	/* PC2 / { 0, 0, 0, 0, 0, 0 }, / PC2 */
142	/* PC1 / { 0, 0, 0, 0, 0, 0 }, / PC1 */
143	/* PC0 / { 0, 0, 0, 0, 0, 0 }, / FDC37C78 DRQFD */
144	},
145
146	/* Port D */
147	{ /* conf ppar psor pdir podr pdat */
148	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 RXD */
149	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 TXD */
150	/* PD29 / { 1, 0, 0, 1, 0, 0 }, / SCC1 RTS */
151	/* PD28 / { 1, 1, 0, 0, 0, 0 }, / SCC2 RXD */
152	/* PD27 / { 1, 1, 0, 1, 0, 0 }, / SCC2 TXD */
153	/* PD26 / { 1, 0, 0, 1, 0, 0 }, / SCC2 RTS */
154	/* PD25 / { 0, 0, 0, 0, 0, 0 }, / PD25 */
155	/* PD24 / { 0, 0, 0, 0, 0, 0 }, / PD24 */
156	/* PD23 / { 0, 0, 0, 0, 0, 0 }, / PD23 */
157	/* PD22 / { 0, 0, 0, 0, 0, 0 }, / PD22 */
158	/* PD21 / { 0, 0, 0, 0, 0, 0 }, / PD21 */
159	/* PD20 / { 0, 0, 0, 0, 0, 0 }, / PD20 */
160	/* PD19 / { 0, 0, 0, 0, 0, 0 }, / PD19 */
161	/* PD18 / { 0, 0, 0, 0, 0, 0 }, / PD18 */
162	/* PD17 / { 0, 0, 0, 0, 0, 0 }, / PD17 */
163	/* PD16 / { 0, 0, 0, 0, 0, 0 }, / PD16 */
164	#if defined(CONFIG_SOFT_I2C)
165	/* PD15 / { 1, 0, 0, 1, 1, 1 }, / I2C SDA */
166	/* PD14 / { 1, 0, 0, 1, 1, 1 }, / I2C SCL */
167	#else
168	#if defined(CONFIG_HARD_I2C)
169	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
170	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
171	#else /* normal I/O port pins */
172	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
173	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
174	#endif
175	#endif
176	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
177	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
178	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
179	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
180	/* PD9 / { 1, 1, 0, 1, 0, 0 }, / SMC1 TXD */
181	/* PD8 / { 1, 1, 0, 0, 0, 0 }, / SMC1 RXD */
182	/* PD7 / { 0, 0, 0, 0, 0, 0 }, / PD7 */
183	/* PD6 / { 0, 0, 0, 0, 0, 0 }, / PD6 */
184	/* PD5 / { 0, 0, 0, 0, 0, 0 }, / PD5 */
185	/* PD4 / { 0, 0, 0, 0, 0, 0 }, / PD4 */
186	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / PD3 */
187	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / PD2 */
188	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / PD1 */
189	/* PD0 / { 0, 0, 0, 0, 0, 0 } / PD0 */
190	}
191	};
192
193	/* ------------------------------------------------------------------------- */
194
195	/* Check Board Identity:
196	*/
197	int checkboard (void)
198	{
199	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
200	return 0;
201	}
202
203	/* ------------------------------------------------------------------------- */
204
205	/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
206	*
207	* This routine performs standard 8260 initialization sequence
208	* and calculates the available memory size. It may be called
209	* several times to try different SDRAM configurations on both
210	* 60x and local buses.
211	*/
212	static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
213	ulong orx, volatile uchar * base)
214	{
215	volatile uchar c = 0xff;
f8cac651 WD	216	volatile uint *sdmr_ptr;
f8cac651 WD	217	volatile uint *orx_ptr;
c83bf6a2	218	ulong maxsize, size;
f8cac651	219	int i;
f8cac651 WD	220
	221	/* We must be able to test a location outsize the maximum legal size
	222	* to find out THAT we are outside; but this address still has to be
	223	* mapped by the controller. That means, that the initial mapping has
	224	* to be (at least) twice as large as the maximum expected size.
	225	*/
	226	maxsize = (1 + (~orx \| 0x7fff)) / 2;
	227
6d0f6bcf	228	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
f8cac651 WD	229	* we are configuring CS1 if base != 0
	230	*/
	231	sdmr_ptr = &memctl->memc_psdmr;
	232	orx_ptr = &memctl->memc_or2;
	233
	234	*orx_ptr = orx;
	235
	236	/*
	237	* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	238	*
	239	* "At system reset, initialization software must set up the
	240	* programmable parameters in the memory controller banks registers
	241	* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	242	* system software should execute the following initialization sequence
	243	* for each SDRAM device.
	244	*
	245	* 1. Issue a PRECHARGE-ALL-BANKS command
	246	* 2. Issue eight CBR REFRESH commands
	247	* 3. Issue a MODE-SET command to initialize the mode register
	248	*
	249	* The initial commands are executed by setting P/LSDMR[OP] and
	250	* accessing the SDRAM with a single-byte transaction."
	251	*
	252	* The appropriate BRx/ORx registers have already been set when we
6d0f6bcf	253	* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
f8cac651 WD	254	*/
	255
	256	*sdmr_ptr = sdmr \| PSDMR_OP_PREA;
	257	*base = c;
	258
	259	*sdmr_ptr = sdmr \| PSDMR_OP_CBRR;
	260	for (i = 0; i < 8; i++)
	261	*base = c;
	262
	263	*sdmr_ptr = sdmr \| PSDMR_OP_MRW;
6d0f6bcf	264	(base + CONFIG_SYS_MRS_OFFS) = c; / setting MR on address lines */
f8cac651 WD	265
	266	*sdmr_ptr = sdmr \| PSDMR_OP_NORM \| PSDMR_RFEN;
	267	*base = c;
	268
c83bf6a2	269	size = get_ram_size((long *)base, maxsize);
f8cac651	270
c83bf6a2	271	*orx_ptr = orx \| ~(size - 1);
f8cac651	272
c83bf6a2	273	return (size);
f8cac651 WD	274	}
f8cac651 WD	275
9973e3c6	276	phys_size_t initdram (int board_type)
f8cac651	277	{
6d0f6bcf	278	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
f8cac651 WD	279	volatile memctl8260_t *memctl = &immap->im_memctl;
f8cac651 WD	280
6d0f6bcf	281	#ifndef CONFIG_SYS_RAMBOOT
f8cac651 WD	282	ulong size8, size9;
	283	#endif
	284	long psize;
	285
	286	psize = 32 * 1024 * 1024;
	287
6d0f6bcf JCPV	288	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
6d0f6bcf JCPV	289	memctl->memc_psrt = CONFIG_SYS_PSRT;
f8cac651	290
6d0f6bcf	291	#ifndef CONFIG_SYS_RAMBOOT
f8cac651 WD	292	/* 60x SDRAM setup:
f8cac651 WD	293	*/
6d0f6bcf JCPV	294	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
	295	(uchar *) CONFIG_SYS_SDRAM_BASE);
	296	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
	297	(uchar *) CONFIG_SYS_SDRAM_BASE);
f8cac651 WD	298
	299	if (size8 < size9) {
	300	psize = size9;
	301	printf ("(60x:9COL) ");
	302	} else {
6d0f6bcf JCPV	303	psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
6d0f6bcf JCPV	304	(uchar *) CONFIG_SYS_SDRAM_BASE);
f8cac651 WD	305	printf ("(60x:8COL) ");
	306	}
	307
6d0f6bcf	308	#endif /* CONFIG_SYS_RAMBOOT */
f8cac651 WD	309
	310	icache_enable ();
	311
	312	return (psize);
	313	}
	314
fcec2eb9	315	#if defined(CONFIG_CMD_DOC)
f8cac651 WD	316	void doc_init (void)
f8cac651 WD	317	{
6d0f6bcf	318	doc_probe (CONFIG_SYS_DOC_BASE);
f8cac651 WD	319	}
f8cac651 WD	320	#endif