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52f52c14 WD |
1 | /* |
2 | * Most of this taken from Redboot hal_platform_setup.h with cleanup | |
3 | * | |
4 | * NOTE: I haven't clean this up considerably, just enough to get it | |
5 | * running. See hal_platform_setup.h for the source. See | |
400558b5 | 6 | * board/cradle/lowlevel_init.S for another PXA250 setup that is |
52f52c14 WD |
7 | * much cleaner. |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <config.h> | |
29 | #include <version.h> | |
30 | #include <asm/arch/pxa-regs.h> | |
31 | ||
6d0f6bcf | 32 | DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE |
52f52c14 WD |
33 | |
34 | /* wait for coprocessor write complete */ | |
35 | .macro CPWAIT reg | |
36 | mrc p15,0,\reg,c2,c0,0 | |
37 | mov \reg,\reg | |
38 | sub pc,pc,#4 | |
39 | .endm | |
40 | ||
41 | _TEXT_BASE: | |
42 | .word TEXT_BASE | |
43 | ||
44 | ||
45 | /* | |
53677ef1 | 46 | * Memory setup |
52f52c14 WD |
47 | */ |
48 | ||
400558b5 WD |
49 | .globl lowlevel_init |
50 | lowlevel_init: | |
52f52c14 WD |
51 | |
52 | mov r10, lr | |
53 | ||
54 | /* Set up GPIO pins first ----------------------------------------- */ | |
55 | ||
56 | ldr r0, =GPSR0 | |
6d0f6bcf | 57 | ldr r1, =CONFIG_SYS_GPSR0_VAL |
52f52c14 WD |
58 | str r1, [r0] |
59 | ||
60 | ldr r0, =GPSR1 | |
6d0f6bcf | 61 | ldr r1, =CONFIG_SYS_GPSR1_VAL |
52f52c14 WD |
62 | str r1, [r0] |
63 | ||
64 | ldr r0, =GPSR2 | |
6d0f6bcf | 65 | ldr r1, =CONFIG_SYS_GPSR2_VAL |
52f52c14 WD |
66 | str r1, [r0] |
67 | ||
68 | ldr r0, =GPCR0 | |
6d0f6bcf | 69 | ldr r1, =CONFIG_SYS_GPCR0_VAL |
52f52c14 WD |
70 | str r1, [r0] |
71 | ||
72 | ldr r0, =GPCR1 | |
6d0f6bcf | 73 | ldr r1, =CONFIG_SYS_GPCR1_VAL |
52f52c14 WD |
74 | str r1, [r0] |
75 | ||
76 | ldr r0, =GPCR2 | |
6d0f6bcf | 77 | ldr r1, =CONFIG_SYS_GPCR2_VAL |
52f52c14 WD |
78 | str r1, [r0] |
79 | ||
80 | ldr r0, =GPDR0 | |
6d0f6bcf | 81 | ldr r1, =CONFIG_SYS_GPDR0_VAL |
52f52c14 WD |
82 | str r1, [r0] |
83 | ||
84 | ldr r0, =GPDR1 | |
6d0f6bcf | 85 | ldr r1, =CONFIG_SYS_GPDR1_VAL |
52f52c14 WD |
86 | str r1, [r0] |
87 | ||
88 | ldr r0, =GPDR2 | |
6d0f6bcf | 89 | ldr r1, =CONFIG_SYS_GPDR2_VAL |
52f52c14 WD |
90 | str r1, [r0] |
91 | ||
92 | ldr r0, =GAFR0_L | |
6d0f6bcf | 93 | ldr r1, =CONFIG_SYS_GAFR0_L_VAL |
52f52c14 WD |
94 | str r1, [r0] |
95 | ||
96 | ldr r0, =GAFR0_U | |
6d0f6bcf | 97 | ldr r1, =CONFIG_SYS_GAFR0_U_VAL |
52f52c14 WD |
98 | str r1, [r0] |
99 | ||
100 | ldr r0, =GAFR1_L | |
6d0f6bcf | 101 | ldr r1, =CONFIG_SYS_GAFR1_L_VAL |
52f52c14 WD |
102 | str r1, [r0] |
103 | ||
104 | ldr r0, =GAFR1_U | |
6d0f6bcf | 105 | ldr r1, =CONFIG_SYS_GAFR1_U_VAL |
52f52c14 WD |
106 | str r1, [r0] |
107 | ||
108 | ldr r0, =GAFR2_L | |
6d0f6bcf | 109 | ldr r1, =CONFIG_SYS_GAFR2_L_VAL |
52f52c14 WD |
110 | str r1, [r0] |
111 | ||
112 | ldr r0, =GAFR2_U | |
6d0f6bcf | 113 | ldr r1, =CONFIG_SYS_GAFR2_U_VAL |
52f52c14 WD |
114 | str r1, [r0] |
115 | ||
116 | ldr r0, =PSSR /* enable GPIO pins */ | |
6d0f6bcf | 117 | ldr r1, =CONFIG_SYS_PSSR_VAL |
52f52c14 WD |
118 | str r1, [r0] |
119 | ||
120 | /* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ | |
6d0f6bcf | 121 | /* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */ |
52f52c14 WD |
122 | /* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ |
123 | /* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ | |
124 | /* */ | |
125 | /* ldr r1, =LED_BLANK */ | |
126 | /* mov r0, #0xFF */ | |
127 | /* str r0, [r1] / turn on hex leds */ | |
128 | /* */ | |
129 | /*loop: */ | |
130 | /* */ | |
131 | /* ldr r0, =0xB0070001 */ | |
53677ef1 WD |
132 | /* ldr r1, =_LED */ |
133 | /* str r0, [r1] / hex display */ | |
52f52c14 WD |
134 | |
135 | ||
136 | /* ---------------------------------------------------------------- */ | |
137 | /* Enable memory interface */ | |
138 | /* */ | |
139 | /* The sequence below is based on the recommended init steps */ | |
140 | /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ | |
141 | /* Chapter 10. */ | |
142 | /* ---------------------------------------------------------------- */ | |
143 | ||
144 | /* ---------------------------------------------------------------- */ | |
145 | /* Step 1: Wait for at least 200 microsedonds to allow internal */ | |
146 | /* clocks to settle. Only necessary after hard reset... */ | |
147 | /* FIXME: can be optimized later */ | |
148 | /* ---------------------------------------------------------------- */ | |
149 | ||
150 | ldr r3, =OSCR /* reset the OS Timer Count to zero */ | |
151 | mov r2, #0 | |
152 | str r2, [r3] | |
153 | ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ | |
154 | /* so 0x300 should be plenty */ | |
155 | 1: | |
156 | ldr r2, [r3] | |
157 | cmp r4, r2 | |
158 | bgt 1b | |
159 | ||
160 | mem_init: | |
161 | ||
8bde7f77 | 162 | ldr r1, =MEMC_BASE /* get memory controller base addr. */ |
52f52c14 WD |
163 | |
164 | /* ---------------------------------------------------------------- */ | |
165 | /* Step 2a: Initialize Asynchronous static memory controller */ | |
166 | /* ---------------------------------------------------------------- */ | |
167 | ||
168 | /* MSC registers: timing, bus width, mem type */ | |
169 | ||
8bde7f77 | 170 | /* MSC0: nCS(0,1) */ |
6d0f6bcf | 171 | ldr r2, =CONFIG_SYS_MSC0_VAL |
8bde7f77 WD |
172 | str r2, [r1, #MSC0_OFFSET] |
173 | ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ | |
52f52c14 | 174 | /* that data latches */ |
8bde7f77 | 175 | /* MSC1: nCS(2,3) */ |
6d0f6bcf | 176 | ldr r2, =CONFIG_SYS_MSC1_VAL |
8bde7f77 WD |
177 | str r2, [r1, #MSC1_OFFSET] |
178 | ldr r2, [r1, #MSC1_OFFSET] | |
52f52c14 WD |
179 | |
180 | /* MSC2: nCS(4,5) */ | |
6d0f6bcf | 181 | ldr r2, =CONFIG_SYS_MSC2_VAL |
8bde7f77 WD |
182 | str r2, [r1, #MSC2_OFFSET] |
183 | ldr r2, [r1, #MSC2_OFFSET] | |
52f52c14 WD |
184 | |
185 | /* ---------------------------------------------------------------- */ | |
186 | /* Step 2b: Initialize Card Interface */ | |
187 | /* ---------------------------------------------------------------- */ | |
188 | ||
189 | /* MECR: Memory Expansion Card Register */ | |
6d0f6bcf | 190 | ldr r2, =CONFIG_SYS_MECR_VAL |
8bde7f77 | 191 | str r2, [r1, #MECR_OFFSET] |
52f52c14 WD |
192 | ldr r2, [r1, #MECR_OFFSET] |
193 | ||
194 | /* MCMEM0: Card Interface slot 0 timing */ | |
6d0f6bcf | 195 | ldr r2, =CONFIG_SYS_MCMEM0_VAL |
8bde7f77 | 196 | str r2, [r1, #MCMEM0_OFFSET] |
52f52c14 WD |
197 | ldr r2, [r1, #MCMEM0_OFFSET] |
198 | ||
8bde7f77 | 199 | /* MCMEM1: Card Interface slot 1 timing */ |
6d0f6bcf | 200 | ldr r2, =CONFIG_SYS_MCMEM1_VAL |
8bde7f77 | 201 | str r2, [r1, #MCMEM1_OFFSET] |
52f52c14 WD |
202 | ldr r2, [r1, #MCMEM1_OFFSET] |
203 | ||
204 | /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ | |
6d0f6bcf | 205 | ldr r2, =CONFIG_SYS_MCATT0_VAL |
8bde7f77 | 206 | str r2, [r1, #MCATT0_OFFSET] |
52f52c14 WD |
207 | ldr r2, [r1, #MCATT0_OFFSET] |
208 | ||
209 | /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ | |
6d0f6bcf | 210 | ldr r2, =CONFIG_SYS_MCATT1_VAL |
8bde7f77 | 211 | str r2, [r1, #MCATT1_OFFSET] |
52f52c14 WD |
212 | ldr r2, [r1, #MCATT1_OFFSET] |
213 | ||
214 | /* MCIO0: Card Interface I/O Space Timing, slot 0 */ | |
6d0f6bcf | 215 | ldr r2, =CONFIG_SYS_MCIO0_VAL |
8bde7f77 | 216 | str r2, [r1, #MCIO0_OFFSET] |
52f52c14 WD |
217 | ldr r2, [r1, #MCIO0_OFFSET] |
218 | ||
219 | /* MCIO1: Card Interface I/O Space Timing, slot 1 */ | |
6d0f6bcf | 220 | ldr r2, =CONFIG_SYS_MCIO1_VAL |
8bde7f77 | 221 | str r2, [r1, #MCIO1_OFFSET] |
52f52c14 WD |
222 | ldr r2, [r1, #MCIO1_OFFSET] |
223 | ||
224 | /* ---------------------------------------------------------------- */ | |
8bde7f77 WD |
225 | /* Step 2c: Write FLYCNFG FIXME: what's that??? */ |
226 | /* ---------------------------------------------------------------- */ | |
52f52c14 | 227 | |
8bde7f77 | 228 | /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ |
52f52c14 WD |
229 | adr r3, mem_init /* r0 <- current position of code */ |
230 | ldr r2, =mem_init | |
231 | cmp r3, r2 /* skip init if in place */ | |
232 | beq initirqs | |
233 | ||
234 | ||
235 | /* ---------------------------------------------------------------- */ | |
8bde7f77 WD |
236 | /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ |
237 | /* ---------------------------------------------------------------- */ | |
52f52c14 WD |
238 | |
239 | /* Before accessing MDREFR we need a valid DRI field, so we set */ | |
240 | /* this to power on defaults + DRI field. */ | |
241 | ||
6d0f6bcf | 242 | ldr r3, =CONFIG_SYS_MDREFR_VAL |
52f52c14 WD |
243 | ldr r2, =0xFFF |
244 | and r3, r3, r2 | |
245 | ldr r4, =0x03ca4000 | |
246 | orr r4, r4, r3 | |
247 | ||
248 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
8bde7f77 | 249 | ldr r4, [r1, #MDREFR_OFFSET] |
52f52c14 WD |
250 | |
251 | ||
252 | /* ---------------------------------------------------------------- */ | |
253 | /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ | |
254 | /* ---------------------------------------------------------------- */ | |
255 | ||
256 | /* Initialize SXCNFG register. Assert the enable bits */ | |
257 | ||
258 | /* Write SXMRS to cause an MRS command to all enabled banks of */ | |
259 | /* synchronous static memory. Note that SXLCR need not be written */ | |
260 | /* at this time. */ | |
261 | ||
262 | /* FIXME: we use async mode for now */ | |
263 | ||
264 | ||
8bde7f77 WD |
265 | /* ---------------------------------------------------------------- */ |
266 | /* Step 4: Initialize SDRAM */ | |
267 | /* ---------------------------------------------------------------- */ | |
52f52c14 WD |
268 | |
269 | /* Step 4a: assert MDREFR:K?RUN and configure */ | |
270 | /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ | |
271 | ||
6d0f6bcf | 272 | ldr r4, =CONFIG_SYS_MDREFR_VAL |
52f52c14 WD |
273 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
274 | ldr r4, [r1, #MDREFR_OFFSET] | |
275 | ||
276 | /* Step 4b: de-assert MDREFR:SLFRSH. */ | |
277 | ||
278 | bic r4, r4, #(MDREFR_SLFRSH) | |
279 | ||
8bde7f77 WD |
280 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
281 | ldr r4, [r1, #MDREFR_OFFSET] | |
52f52c14 WD |
282 | |
283 | ||
284 | /* Step 4c: assert MDREFR:E1PIN and E0PIO */ | |
285 | ||
286 | orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) | |
287 | ||
8bde7f77 WD |
288 | str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
289 | ldr r4, [r1, #MDREFR_OFFSET] | |
52f52c14 WD |
290 | |
291 | ||
292 | /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ | |
293 | /* configure but not enable each SDRAM partition pair. */ | |
294 | ||
6d0f6bcf | 295 | ldr r4, =CONFIG_SYS_MDCNFG_VAL |
52f52c14 WD |
296 | bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) |
297 | ||
8bde7f77 WD |
298 | str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ |
299 | ldr r4, [r1, #MDCNFG_OFFSET] | |
52f52c14 WD |
300 | |
301 | ||
302 | /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ | |
303 |