[people/ms/u-boot.git] / board / dave / PPChameleonEVB / PPChameleonEVB.c

/*
 * (C) Copyright 2003
 * DAVE Srl
 * http://www.dave-tech.it
 * http://www.wawnet.biz
 * mailto:info@wawnet.biz
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/* Prototypes */
int gunzip(void *, int, unsigned char *, int *);


int board_early_init_f (void)
{
	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
	out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
#if 1 /* test-only */
	mtebc (epcr, 0xa8400000); /* ebc always driven */
#else
	mtebc (epcr, 0x28400000); /* ebc in high-z */
#endif

	return 0;
}


/* ------------------------------------------------------------------------- */

int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}

extern flash_info_t flash_info[];	/* info for FLASH chips */

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	/* adjust flash start and size as well as the offset */
	gd->bd->bi_flashstart = 0 - flash_info[0].size;
	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
#if 0
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	volatile unsigned char *duart0_mcr =
		(unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr =
		(unsigned char *)((ulong)DUART1_BA + 4);

	bd_t *bd = gd->bd;
	char *	tmp;                    /* Temporary char pointer      */
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long cntrl0Reg;

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

#endif

#if 0
	/*
	 * Enable power on PS/2 interface
	 */
	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;
#endif
	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	unsigned char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming PPChameleonEVB");
	} else {
		puts(str);
	}

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0 /* test-only */
	for (;;) {
		NAND_DISABLE_CE(1);
		udelay(100);
		NAND_ENABLE_CE(1);
		udelay(100);
	}
#endif
#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
extern ulong
nand_probe(ulong physadr);

void
nand_init(void)
{
	ulong totlen = 0;

#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
	totlen += nand_probe (CFG_NAND0_BASE);
#endif	/* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */

	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
	totlen += nand_probe (CFG_NAND1_BASE);

	printf ("%4lu MB\n", totlen >>20);
}
#endif
Commit	Line	Data
12f34241	1	/*
180d3f74 WD	2	* (C) Copyright 2003
	3	* DAVE Srl
	4	* http://www.dave-tech.it
	5	* http://www.wawnet.biz
	6	* mailto:info@wawnet.biz
12f34241 WD	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <asm/processor.h>
	29	#include <command.h>
	30	#include <malloc.h>
	31
	32	/* ------------------------------------------------------------------------- */
	33
	34	#if 0
	35	#define FPGA_DEBUG
	36	#endif
	37
	38	/* fpga configuration data - gzip compressed and generated by bin2c */
	39	const unsigned char fpgadata[] =
	40	{
	41	#include "fpgadata.c"
	42	};
	43
	44	/*
	45	* include common fpga code (for esd boards)
	46	*/
	47	#include "../common/fpga.c"
	48
	49
	50	/* Prototypes */
	51	int gunzip(void , int, unsigned char , int *);
	52
	53
c837dcb1	54	int board_early_init_f (void)
12f34241 WD	55	{
12f34241 WD	56	out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
42d1f039	57	out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
12f34241 WD	58
	59	/*
	60	* IRQ 0-15 405GP internally generated; active high; level sensitive
	61	* IRQ 16 405GP internally generated; active low; level sensitive
	62	* IRQ 17-24 RESERVED
	63	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	64	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	65	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	66	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	67	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	68	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	69	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	70	*/
	71	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	72	mtdcr(uicer, 0x00000000); /* disable all ints */
	73	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
4654af27	74	mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
12f34241 WD	75	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	76	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	77	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	78
	79	/*
	80	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	81	*/
	82	#if 1 /* test-only */
	83	mtebc (epcr, 0xa8400000); /* ebc always driven */
	84	#else
	85	mtebc (epcr, 0x28400000); /* ebc in high-z */
	86	#endif
	87
	88	return 0;
	89	}
	90
	91
	92	/* ------------------------------------------------------------------------- */
	93
	94	int misc_init_f (void)
	95	{
	96	return 0; /* dummy implementation */
	97	}
	98
46a414dc	99	extern flash_info_t flash_info[]; /* info for FLASH chips */
12f34241 WD	100
	101	int misc_init_r (void)
	102	{
12f34241	103	DECLARE_GLOBAL_DATA_PTR;
46a414dc WD	104
	105	/* adjust flash start and size as well as the offset */
	106	gd->bd->bi_flashstart = 0 - flash_info[0].size;
	107	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
12f34241 WD	108	#if 0
	109	volatile unsigned short *fpga_mode =
	110	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	111	volatile unsigned char *duart0_mcr =
	112	(unsigned char *)((ulong)DUART0_BA + 4);
	113	volatile unsigned char *duart1_mcr =
	114	(unsigned char *)((ulong)DUART1_BA + 4);
	115
	116	bd_t *bd = gd->bd;
	117	char * tmp; /* Temporary char pointer */
	118	unsigned char *dst;
	119	ulong len = sizeof(fpgadata);
	120	int status;
	121	int index;
	122	int i;
	123	unsigned long cntrl0Reg;
	124
	125	dst = malloc(CFG_FPGA_MAX_SIZE);
	126	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar )fpgadata, (int )&len) != 0) {
	127	printf ("GUNZIP ERROR - must RESET board to recover\n");
	128	do_reset (NULL, 0, 0, NULL);
	129	}
	130
	131	status = fpga_boot(dst, len);
	132	if (status != 0) {
	133	printf("\nFPGA: Booting failed ");
	134	switch (status) {
	135	case ERROR_FPGA_PRG_INIT_LOW:
	136	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	137	break;
	138	case ERROR_FPGA_PRG_INIT_HIGH:
	139	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	140	break;
	141	case ERROR_FPGA_PRG_DONE:
	142	printf("(Timeout: DONE not high after programming FPGA)\n ");
	143	break;
	144	}
	145
	146	/* display infos on fpgaimage */
	147	index = 15;
	148	for (i=0; i<4; i++) {
	149	len = dst[index];
	150	printf("FPGA: %s\n", &(dst[index+1]));
	151	index += len+3;
	152	}
	153	putc ('\n');
	154	/* delayed reboot */
	155	for (i=20; i>0; i--) {
	156	printf("Rebooting in %2d seconds \r",i);
	157	for (index=0;index<1000;index++)
	158	udelay(1000);
	159	}
	160	putc ('\n');
	161	do_reset(NULL, 0, 0, NULL);
	162	}
	163
	164	puts("FPGA: ");
	165
	166	/* display infos on fpgaimage */
	167	index = 15;
	168	for (i=0; i<4; i++) {
	169	len = dst[index];
	170	printf("%s ", &(dst[index+1]));
	171	index += len+3;
172	}
173	putc ('\n');
174
175	free(dst);
176
177	/*
178	* Reset FPGA via FPGA_DATA pin
179	*/
180	SET_FPGA(FPGA_PRG \| FPGA_CLK);
181	udelay(1000); /* wait 1ms */
182	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
183	udelay(1000); /* wait 1ms */
184
185	#endif
186
187	#if 0
188	/*
189	* Enable power on PS/2 interface
190	*/
191	*fpga_mode \|= CFG_FPGA_CTRL_PS2_RESET;
192
193	/*
194	* Enable interrupts in exar duart mcr[3]
195	*/
196	*duart0_mcr = 0x08;
197	*duart1_mcr = 0x08;
198	#endif
12f34241 WD	199	return (0);
	200	}
	201
	202
	203	/*
	204	* Check Board Identity:
	205	*/
	206
	207	int checkboard (void)
	208	{
	209	unsigned char str[64];
	210	int i = getenv_r ("serial#", str, sizeof(str));
	211
	212	puts ("Board: ");
	213
	214	if (i == -1) {
	215	puts ("### No HW ID - assuming PPChameleonEVB");
	216	} else {
	217	puts(str);
	218	}
	219
	220	putc ('\n');
	221
	222	return 0;
	223	}
	224
	225	/* ------------------------------------------------------------------------- */
	226
	227	long int initdram (int board_type)
	228	{
	229	unsigned long val;
	230
	231	mtdcr(memcfga, mem_mb0cf);
	232	val = mfdcr(memcfgd);
	233
	234	#if 0 /* test-only */
	235	for (;;) {
	236	NAND_DISABLE_CE(1);
	237	udelay(100);
	238	NAND_ENABLE_CE(1);
	239	udelay(100);
	240	}
	241	#endif
	242	#if 0
	243	printf("\nmb0cf=%x\n", val); /* test-only */
	244	printf("strap=%x\n", mfdcr(strap)); /* test-only */
	245	#endif
	246
	247	return (410241024 << ((val & 0x000e0000) >> 17));
	248	}
	249
	250	/* ------------------------------------------------------------------------- */
	251
	252	int testdram (void)
	253	{
	254	/* TODO: XXX XXX XXX */
	255	printf ("test: 16 MB - ok\n");
	256
	257	return (0);
	258	}
	259
	260	/* ------------------------------------------------------------------------- */
	261
	262	#if (CONFIG_COMMANDS & CFG_CMD_NAND)
a43278a4	263	extern ulong
12f34241 WD	264	nand_probe(ulong physadr);
	265
	266	void
	267	nand_init(void)
	268	{
fbe4b5cb	269	ulong totlen = 0;
a43278a4	270
fbe4b5cb WD	271	#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) \|\| \
fbe4b5cb WD	272	(CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
4d816774	273	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
fbe4b5cb WD	274	totlen += nand_probe (CFG_NAND0_BASE);
fbe4b5cb WD	275	#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
4d816774 WD	276
4d816774 WD	277	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
a43278a4 WD	278	totlen += nand_probe (CFG_NAND1_BASE);
	279
	280	printf ("%4lu MB\n", totlen >>20);
12f34241 WD	281	}
12f34241 WD	282	#endif