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rename CFG_ macros to CONFIG_SYS
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1/*
2 * (C) Copyright 2001-2003
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <command.h>
28
29/* ------------------------------------------------------------------------- */
30
31#ifdef FPGA_DEBUG
32#define DBG(x...) printf(x)
33#else
34#define DBG(x...)
35#endif /* DEBUG */
36
37#define MAX_ONES 226
38
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JCPV
39#ifdef CONFIG_SYS_FPGA_PRG
40# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
41# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
42# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
43# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
44# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
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45#else
46# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
47# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
48# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
49# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
50# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
51#endif
52
53#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
54#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
55#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
56
57#define SET_FPGA(data) out32(GPIO0_OR, data)
58
59#define FPGA_WRITE_1 { \
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60 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
61 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
62 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
63 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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64
65#define FPGA_WRITE_0 { \
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66 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
67 SET_FPGA(FPGA_PRG); /* set data to 0 */ \
68 SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
69 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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70
71#if 0
72static int fpga_boot (unsigned char *fpgadata, int size)
73{
74 int i, index, len;
75 int count;
76
6d0f6bcf 77#ifdef CONFIG_SYS_FPGA_SPARTAN2
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78 int j;
79#else
80 unsigned char b;
81 int bit;
82#endif
83
84 /* display infos on fpgaimage */
85 index = 15;
86 for (i = 0; i < 4; i++) {
87 len = fpgadata[index];
88 DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
89 index += len + 3;
90 }
91
6d0f6bcf 92#ifdef CONFIG_SYS_FPGA_SPARTAN2
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93 /* search for preamble 0xFFFFFFFF */
94 while (1) {
95 if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
96 && (fpgadata[index + 2] == 0xff)
97 && (fpgadata[index + 3] == 0xff))
98 break; /* preamble found */
99 else
100 index++;
101 }
102#else
103 /* search for preamble 0xFF2X */
104 for (index = 0; index < size - 1; index++) {
105 if ((fpgadata[index] == 0xff)
106 && ((fpgadata[index + 1] & 0xf0) == 0x30))
107 break;
108 }
109 index += 2;
110#endif
111
112 DBG ("FPGA: configdata starts at position 0x%x\n", index);
113 DBG ("FPGA: length of fpga-data %d\n", size - index);
114
115 /*
116 * Setup port pins for fpga programming
117 */
118 out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
119 out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
120 out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
121
122 DBG ("%s, ",
123 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
124 DBG ("%s\n",
125 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
126
127 /*
128 * Init fpga by asserting and deasserting PROGRAM*
129 */
130 SET_FPGA (FPGA_CLK | FPGA_DATA);
131
132 /* Wait for FPGA init line low */
133 count = 0;
134 while (in32 (GPIO0_IR) & FPGA_INIT) {
135 udelay (1000); /* wait 1ms */
136 /* Check for timeout - 100us max, so use 3ms */
137 if (count++ > 3) {
138 DBG ("FPGA: Booting failed!\n");
139 return ERROR_FPGA_PRG_INIT_LOW;
140 }
141 }
142
143 DBG ("%s, ",
144 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
145 DBG ("%s\n",
146 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
147
148 /* deassert PROGRAM* */
149 SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
150
151 /* Wait for FPGA end of init period . */
152 count = 0;
153 while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
154 udelay (1000); /* wait 1ms */
155 /* Check for timeout */
156 if (count++ > 3) {
157 DBG ("FPGA: Booting failed!\n");
158 return ERROR_FPGA_PRG_INIT_HIGH;
159 }
160 }
161
162 DBG ("%s, ",
163 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
164 DBG ("%s\n",
165 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
166
167 DBG ("write configuration data into fpga\n");
168 /* write configuration-data into fpga... */
169
6d0f6bcf 170#ifdef CONFIG_SYS_FPGA_SPARTAN2
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171 /*
172 * Load uncompressed image into fpga
173 */
174 for (i = index; i < size; i++) {
175 for (j = 0; j < 8; j++) {
176 if ((fpgadata[i] & 0x80) == 0x80) {
177 FPGA_WRITE_1;
178 } else {
179 FPGA_WRITE_0;
180 }
181 fpgadata[i] <<= 1;
182 }
183 }
6d0f6bcf 184#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */
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185 /* send 0xff 0x20 */
186 FPGA_WRITE_1;
187 FPGA_WRITE_1;
188 FPGA_WRITE_1;
189 FPGA_WRITE_1;
190 FPGA_WRITE_1;
191 FPGA_WRITE_1;
192 FPGA_WRITE_1;
193 FPGA_WRITE_1;
194 FPGA_WRITE_0;
195 FPGA_WRITE_0;
196 FPGA_WRITE_1;
197 FPGA_WRITE_0;
198 FPGA_WRITE_0;
199 FPGA_WRITE_0;
200 FPGA_WRITE_0;
201 FPGA_WRITE_0;
202
203 /*
204 ** Bit_DeCompression
205 ** Code 1 .. maxOnes : n '1's followed by '0'
206 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
207 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
208 ** 255 : '1'
209 */
210
211 for (i = index; i < size; i++) {
212 b = fpgadata[i];
213 if ((b >= 1) && (b <= MAX_ONES)) {
214 for (bit = 0; bit < b; bit++) {
215 FPGA_WRITE_1;
216 }
217 FPGA_WRITE_0;
218 } else if (b == (MAX_ONES + 1)) {
219 for (bit = 1; bit < b; bit++) {
220 FPGA_WRITE_1;
221 }
222 } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
223 for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
224 FPGA_WRITE_0;
225 }
226 FPGA_WRITE_1;
227 } else if (b == 255) {
228 FPGA_WRITE_1;
229 }
230 }
6d0f6bcf 231#endif /* CONFIG_SYS_FPGA_SPARTAN2 */
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232
233 DBG ("%s, ",
234 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
235 DBG ("%s\n",
236 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
237
238 /*
239 * Check if fpga's DONE signal - correctly booted ?
240 */
241
242 /* Wait for FPGA end of programming period . */
243 count = 0;
244 while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
245 udelay (1000); /* wait 1ms */
246 /* Check for timeout */
247 if (count++ > 3) {
248 DBG ("FPGA: Booting failed!\n");
249 return ERROR_FPGA_PRG_DONE;
250 }
251 }
252
253 DBG ("FPGA: Booting successful!\n");
254 return 0;
255}
256#endif /* 0 */