[people/ms/u-boot.git] / board / dbau1x00 / dbau1x00.c

/*
 * (C) Copyright 2003
 * Thomas.Lange@corelatus.se
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>

phys_size_t initdram(int board_type)
{
	/* Sdram is setup by assembler code */
	/* If memory could be changed, we should return the true value here */
	return MEM_SIZE*1024*1024;
}

#define BCSR_PCMCIA_PC0DRVEN		0x0010
#define BCSR_PCMCIA_PC0RST		0x0080

/* In cpu/mips/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );

int checkboard (void)
{
#ifdef CONFIG_IDE_PCMCIA
	u16 status;
	volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
#endif	/* CONFIG_IDE_PCMCIA */
	volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
	u32 proc_id;

	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */

	proc_id = read_c0_prid();

	switch (proc_id >> 24) {
	case 0:
		puts ("Board: Merlot (DbAu1000)\n");
		printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	case 1:
		puts ("Board: DbAu1500\n");
		printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	case 2:
		puts ("Board: DbAu1100\n");
		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	case 3:
		puts ("Board: DbAu1550\n");
		printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	default:
		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
	}

	set_io_port_base(0);

#ifdef CONFIG_IDE_PCMCIA
	/* Enable 3.3 V on slot 0 ( VCC )
	   No 5V */
	status = 4;
	*pcmcia_bcsr = status;

	status |= BCSR_PCMCIA_PC0DRVEN;
	*pcmcia_bcsr = status;
	au_sync();

	udelay(300*1000);

	status |= BCSR_PCMCIA_PC0RST;
	*pcmcia_bcsr = status;
	au_sync();

	udelay(100*1000);

	/* PCMCIA is on a 36 bit physical address.
	   We need to map it into a 32 bit addresses */

#if 0
	/* We dont need theese unless we run whole pcmcia package */
	write_one_tlb(20,                 /* index */
		      0x01ffe000,         /* Pagemask, 16 MB pages */
		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
		      0x3C000017,         /* Lo0 */
		      0x3C200017);        /* Lo1 */

	write_one_tlb(21,                   /* index */
		      0x01ffe000,           /* Pagemask, 16 MB pages */
		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
		      0x3D000017,           /* Lo0 */
		      0x3D200017);          /* Lo1 */
#endif	/* 0 */
	write_one_tlb(22,                   /* index */
		      0x01ffe000,           /* Pagemask, 16 MB pages */
		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
		      0x3E000017,           /* Lo0 */
		      0x3E200017);          /* Lo1 */
#endif	/* CONFIG_IDE_PCMCIA */

	/* Release reset of ethernet PHY chips */
	/* Always do this, because linux does not know about it */
	*phy = 3;

	return 0;
}
Commit	Line	Data
5da627a4 WD	1	/*
	2	* (C) Copyright 2003
	3	* Thomas.Lange@corelatus.se
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <command.h>
	26	#include <asm/au1x00.h>
	27	#include <asm/mipsregs.h>
5c15010e	28	#include <asm/io.h>
5da627a4	29
9973e3c6	30	phys_size_t initdram(int board_type)
5da627a4 WD	31	{
	32	/* Sdram is setup by assembler code */
	33	/* If memory could be changed, we should return the true value here */
ff36fd85	34	return MEM_SIZE10241024;
5da627a4 WD	35	}
	36
	37	#define BCSR_PCMCIA_PC0DRVEN 0x0010
	38	#define BCSR_PCMCIA_PC0RST 0x0080
	39
	40	/* In cpu/mips/cpu.c */
	41	void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
	42
	43	int checkboard (void)
	44	{
c3d2b4b4	45	#ifdef CONFIG_IDE_PCMCIA
5da627a4	46	u16 status;
ff36fd85	47	volatile u32 pcmcia_bcsr = (u32)(DB1XX0_BCSR_ADDR+0x10);
c3d2b4b4	48	#endif /* CONFIG_IDE_PCMCIA */
ff36fd85	49	volatile u32 phy = (u32)(DB1XX0_BCSR_ADDR+0xC);
5da627a4 WD	50	volatile u32 sys_counter = (volatile u32)SYS_COUNTER_CNTRL;
	51	u32 proc_id;
	52
	53	sys_counter = 0x100; / Enable 32 kHz oscillator for RTC/TOY */
	54
e2ad8426	55	proc_id = read_c0_prid();
5da627a4	56
a2663ea4	57	switch (proc_id >> 24) {
5da627a4	58	case 0:
a2663ea4 WD	59	puts ("Board: Merlot (DbAu1000)\n");
	60	printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
	61	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	62	break;
	63	case 1:
	64	puts ("Board: DbAu1500\n");
	65	printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
	66	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	67	break;
	68	case 2:
	69	puts ("Board: DbAu1100\n");
	70	printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
	71	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	72	break;
ff36fd85 WD	73	case 3:
	74	puts ("Board: DbAu1550\n");
	75	printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
	76	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	77	break;
5da627a4	78	default:
a2663ea4	79	printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
5da627a4	80	}
5c15010e JCPV	81
	82	set_io_port_base(0);
	83
5da627a4 WD	84	#ifdef CONFIG_IDE_PCMCIA
	85	/* Enable 3.3 V on slot 0 ( VCC )
	86	No 5V */
	87	status = 4;
	88	*pcmcia_bcsr = status;
	89
	90	status \|= BCSR_PCMCIA_PC0DRVEN;
	91	*pcmcia_bcsr = status;
	92	au_sync();
	93
	94	udelay(300*1000);
	95
	96	status \|= BCSR_PCMCIA_PC0RST;
	97	*pcmcia_bcsr = status;
	98	au_sync();
	99
	100	udelay(100*1000);
	101
	102	/* PCMCIA is on a 36 bit physical address.
	103	We need to map it into a 32 bit addresses */
	104
	105	#if 0
	106	/* We dont need theese unless we run whole pcmcia package */
	107	write_one_tlb(20, /* index */
	108	0x01ffe000, /* Pagemask, 16 MB pages */
6d0f6bcf	109	CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
5da627a4 WD	110	0x3C000017, /* Lo0 */
	111	0x3C200017); /* Lo1 */
	112
	113	write_one_tlb(21, /* index */
	114	0x01ffe000, /* Pagemask, 16 MB pages */
6d0f6bcf	115	CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
5da627a4 WD	116	0x3D000017, /* Lo0 */
5da627a4 WD	117	0x3D200017); /* Lo1 */
697037fe	118	#endif /* 0 */
5da627a4 WD	119	write_one_tlb(22, /* index */
5da627a4 WD	120	0x01ffe000, /* Pagemask, 16 MB pages */
6d0f6bcf	121	CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
5da627a4 WD	122	0x3E000017, /* Lo0 */
5da627a4 WD	123	0x3E200017); /* Lo1 */
697037fe	124	#endif /* CONFIG_IDE_PCMCIA */
5da627a4 WD	125
	126	/* Release reset of ethernet PHY chips */
	127	/* Always do this, because linux does not know about it */
	128	*phy = 3;
	129
	130	return 0;
5da627a4	131	}