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fc102728 MV |
1 | /* |
2 | * DENX M28 module | |
3 | * | |
4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
5 | * on behalf of DENX Software Engineering GmbH | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <asm/gpio.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/arch/imx-regs.h> | |
30 | #include <asm/arch/iomux-mx28.h> | |
31 | #include <asm/arch/clock.h> | |
32 | #include <asm/arch/sys_proto.h> | |
33 | #include <linux/mii.h> | |
34 | #include <miiphy.h> | |
35 | #include <netdev.h> | |
36 | #include <errno.h> | |
37 | ||
38 | DECLARE_GLOBAL_DATA_PTR; | |
39 | ||
40 | /* | |
41 | * Functions | |
42 | */ | |
43 | int board_early_init_f(void) | |
44 | { | |
45 | /* IO0 clock at 480MHz */ | |
46 | mx28_set_ioclk(MXC_IOCLK0, 480000); | |
47 | /* IO1 clock at 480MHz */ | |
48 | mx28_set_ioclk(MXC_IOCLK1, 480000); | |
49 | ||
50 | /* SSP0 clock at 96MHz */ | |
51 | mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); | |
52 | /* SSP2 clock at 96MHz */ | |
53 | mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); | |
54 | ||
55 | return 0; | |
56 | } | |
57 | ||
58 | int board_init(void) | |
59 | { | |
60 | /* Adress of boot parameters */ | |
61 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
3a4ce833 MV |
66 | #define HW_DIGCTRL_SCRATCH0 0x8001c280 |
67 | #define HW_DIGCTRL_SCRATCH1 0x8001c290 | |
fc102728 MV |
68 | int dram_init(void) |
69 | { | |
3a4ce833 MV |
70 | uint32_t sz[2]; |
71 | ||
72 | sz[0] = readl(HW_DIGCTRL_SCRATCH0); | |
73 | sz[1] = readl(HW_DIGCTRL_SCRATCH1); | |
74 | ||
75 | if (sz[0] != sz[1]) { | |
76 | printf("MX28:\n" | |
77 | "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" | |
78 | "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" | |
79 | "verify these two registers contain valid RAM size!\n"); | |
80 | hang(); | |
81 | } | |
82 | ||
83 | gd->ram_size = sz[0]; | |
fc102728 MV |
84 | return 0; |
85 | } | |
86 | ||
87 | #ifdef CONFIG_CMD_MMC | |
88 | static int m28_mmc_wp(int id) | |
89 | { | |
90 | if (id != 0) { | |
91 | printf("MXS MMC: Invalid card selected (card id = %d)\n", id); | |
92 | return 1; | |
93 | } | |
94 | ||
95 | return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10); | |
96 | } | |
97 | ||
98 | int board_mmc_init(bd_t *bis) | |
99 | { | |
100 | /* Configure WP as output */ | |
101 | gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); | |
102 | ||
103 | return mxsmmc_initialize(bis, 0, m28_mmc_wp); | |
104 | } | |
105 | #endif | |
106 | ||
107 | #ifdef CONFIG_CMD_NET | |
108 | ||
109 | #define MII_OPMODE_STRAP_OVERRIDE 0x16 | |
110 | #define MII_PHY_CTRL1 0x1e | |
111 | #define MII_PHY_CTRL2 0x1f | |
112 | ||
113 | int fecmxc_mii_postcall(int phy) | |
114 | { | |
115 | miiphy_write("FEC1", phy, MII_BMCR, 0x9000); | |
116 | miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); | |
117 | if (phy == 3) | |
118 | miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); | |
119 | return 0; | |
120 | } | |
121 | ||
122 | int board_eth_init(bd_t *bis) | |
123 | { | |
124 | struct mx28_clkctrl_regs *clkctrl_regs = | |
125 | (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; | |
126 | struct eth_device *dev; | |
127 | int ret; | |
128 | ||
129 | ret = cpu_eth_init(bis); | |
130 | ||
131 | clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, | |
132 | CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, | |
133 | CLKCTRL_ENET_TIME_SEL_RMII_CLK); | |
134 | ||
135 | ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); | |
136 | if (ret) { | |
137 | printf("FEC MXS: Unable to init FEC0\n"); | |
138 | return ret; | |
139 | } | |
140 | ||
141 | ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); | |
142 | if (ret) { | |
143 | printf("FEC MXS: Unable to init FEC1\n"); | |
144 | return ret; | |
145 | } | |
146 | ||
147 | dev = eth_get_dev_by_name("FEC0"); | |
148 | if (!dev) { | |
149 | printf("FEC MXS: Unable to get FEC0 device entry\n"); | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
153 | ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); | |
154 | if (ret) { | |
155 | printf("FEC MXS: Unable to register FEC0 mii postcall\n"); | |
156 | return ret; | |
157 | } | |
158 | ||
159 | dev = eth_get_dev_by_name("FEC1"); | |
160 | if (!dev) { | |
161 | printf("FEC MXS: Unable to get FEC1 device entry\n"); | |
162 | return -EINVAL; | |
163 | } | |
164 | ||
165 | ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); | |
166 | if (ret) { | |
167 | printf("FEC MXS: Unable to register FEC1 mii postcall\n"); | |
168 | return ret; | |
169 | } | |
170 | ||
171 | return ret; | |
172 | } | |
173 | ||
174 | #ifdef CONFIG_M28_FEC_MAC_IN_OCOTP | |
175 | ||
176 | #define MXS_OCOTP_MAX_TIMEOUT 1000000 | |
177 | void imx_get_mac_from_fuse(char *mac) | |
178 | { | |
179 | struct mx28_ocotp_regs *ocotp_regs = | |
180 | (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; | |
181 | uint32_t data; | |
182 | ||
183 | memset(mac, 0, 6); | |
184 | ||
185 | writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); | |
186 | ||
187 | if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, | |
188 | MXS_OCOTP_MAX_TIMEOUT)) { | |
189 | printf("MXS FEC: Can't get MAC from OCOTP\n"); | |
190 | return; | |
191 | } | |
192 | ||
193 | data = readl(&ocotp_regs->hw_ocotp_cust0); | |
194 | ||
195 | mac[0] = 0x00; | |
196 | mac[1] = 0x04; | |
197 | mac[2] = (data >> 24) & 0xff; | |
198 | mac[3] = (data >> 16) & 0xff; | |
199 | mac[4] = (data >> 8) & 0xff; | |
200 | mac[5] = data & 0xff; | |
201 | } | |
202 | #else | |
203 | void imx_get_mac_from_fuse(char *mac) | |
204 | { | |
205 | memset(mac, 0, 6); | |
206 | } | |
207 | #endif | |
208 | ||
209 | #endif |