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0f83b365 MV |
1 | /* |
2 | * DENX M53 module | |
3 | * | |
4 | * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
0f83b365 MV |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/arch/imx-regs.h> | |
0f83b365 MV |
12 | #include <asm/arch/sys_proto.h> |
13 | #include <asm/arch/crm_regs.h> | |
14 | #include <asm/arch/clock.h> | |
3fec2c67 | 15 | #include <asm/arch/iomux-mx53.h> |
502a710f | 16 | #include <asm/imx-common/mx5_video.h> |
9f2ec3f5 | 17 | #include <asm/spl.h> |
0f83b365 MV |
18 | #include <asm/errno.h> |
19 | #include <netdev.h> | |
20 | #include <i2c.h> | |
21 | #include <mmc.h> | |
22 | #include <spl.h> | |
23 | #include <fsl_esdhc.h> | |
24 | #include <asm/gpio.h> | |
e162c6b1 | 25 | #include <usb/ehci-ci.h> |
502a710f MV |
26 | #include <linux/fb.h> |
27 | #include <ipu_pixfmt.h> | |
28 | ||
29 | /* Special MXCFB sync flags are here. */ | |
30 | #include "../drivers/video/mxcfb.h" | |
0f83b365 MV |
31 | |
32 | DECLARE_GLOBAL_DATA_PTR; | |
33 | ||
97334c66 MV |
34 | static uint32_t mx53_dram_size[2]; |
35 | ||
36 | phys_size_t get_effective_memsize(void) | |
0f83b365 | 37 | { |
97334c66 MV |
38 | /* |
39 | * WARNING: We must override get_effective_memsize() function here | |
40 | * to report only the size of the first DRAM bank. This is to make | |
41 | * U-Boot relocator place U-Boot into valid memory, that is, at the | |
42 | * end of the first DRAM bank. If we did not override this function | |
43 | * like so, U-Boot would be placed at the address of the first DRAM | |
44 | * bank + total DRAM size - sizeof(uboot), which in the setup where | |
45 | * each DRAM bank contains 512MiB of DRAM would result in placing | |
46 | * U-Boot into invalid memory area close to the end of the first | |
47 | * DRAM bank. | |
48 | */ | |
49 | return mx53_dram_size[0]; | |
50 | } | |
0f83b365 | 51 | |
97334c66 MV |
52 | int dram_init(void) |
53 | { | |
54 | mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); | |
55 | mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); | |
0f83b365 | 56 | |
97334c66 | 57 | gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; |
0f83b365 MV |
58 | |
59 | return 0; | |
60 | } | |
97334c66 | 61 | |
0f83b365 MV |
62 | void dram_init_banksize(void) |
63 | { | |
64 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
97334c66 | 65 | gd->bd->bi_dram[0].size = mx53_dram_size[0]; |
0f83b365 MV |
66 | |
67 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
97334c66 | 68 | gd->bd->bi_dram[1].size = mx53_dram_size[1]; |
0f83b365 MV |
69 | } |
70 | ||
71 | static void setup_iomux_uart(void) | |
72 | { | |
3fec2c67 BT |
73 | static const iomux_v3_cfg_t uart_pads[] = { |
74 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, | |
75 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, | |
76 | }; | |
77 | ||
78 | imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); | |
0f83b365 MV |
79 | } |
80 | ||
81 | #ifdef CONFIG_USB_EHCI_MX5 | |
82 | int board_ehci_hcd_init(int port) | |
83 | { | |
84 | if (port == 0) { | |
85 | /* USB OTG PWRON */ | |
3fec2c67 BT |
86 | imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, |
87 | PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); | |
88 | gpio_direction_output(IMX_GPIO_NR(1, 4), 0); | |
0f83b365 MV |
89 | |
90 | /* USB OTG Over Current */ | |
3fec2c67 | 91 | imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); |
0f83b365 MV |
92 | } else if (port == 1) { |
93 | /* USB Host PWRON */ | |
3fec2c67 BT |
94 | imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, |
95 | PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); | |
96 | gpio_direction_output(IMX_GPIO_NR(1, 2), 0); | |
0f83b365 MV |
97 | |
98 | /* USB Host Over Current */ | |
3fec2c67 | 99 | imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); |
0f83b365 MV |
100 | } |
101 | ||
102 | return 0; | |
103 | } | |
104 | #endif | |
105 | ||
106 | static void setup_iomux_fec(void) | |
107 | { | |
3fec2c67 BT |
108 | static const iomux_v3_cfg_t fec_pads[] = { |
109 | /* MDIO pads */ | |
110 | NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | | |
111 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), | |
112 | NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), | |
113 | ||
114 | /* FEC 0 pads */ | |
115 | NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, | |
116 | PAD_CTL_HYS | PAD_CTL_PKE), | |
117 | NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, | |
118 | PAD_CTL_HYS | PAD_CTL_PKE), | |
119 | NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, | |
120 | PAD_CTL_HYS | PAD_CTL_PKE), | |
121 | NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), | |
122 | NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, | |
123 | PAD_CTL_HYS | PAD_CTL_PKE), | |
124 | NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, | |
125 | PAD_CTL_HYS | PAD_CTL_PKE), | |
126 | NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), | |
127 | NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), | |
128 | ||
129 | /* FEC 1 pads */ | |
130 | NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, | |
131 | PAD_CTL_HYS | PAD_CTL_PKE), | |
132 | NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER, | |
133 | PAD_CTL_HYS | PAD_CTL_PKE), | |
134 | NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, | |
135 | PAD_CTL_HYS | PAD_CTL_PKE), | |
136 | NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, | |
137 | PAD_CTL_HYS | PAD_CTL_PKE), | |
138 | NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, | |
139 | PAD_CTL_HYS | PAD_CTL_PKE), | |
140 | NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), | |
141 | NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, | |
142 | PAD_CTL_HYS | PAD_CTL_PKE), | |
143 | NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), | |
144 | }; | |
145 | ||
146 | imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); | |
0f83b365 MV |
147 | } |
148 | ||
149 | #ifdef CONFIG_FSL_ESDHC | |
150 | struct fsl_esdhc_cfg esdhc_cfg = { | |
151 | MMC_SDHC1_BASE_ADDR, | |
152 | }; | |
153 | ||
154 | int board_mmc_getcd(struct mmc *mmc) | |
155 | { | |
3fec2c67 | 156 | imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); |
0f83b365 MV |
157 | gpio_direction_input(IMX_GPIO_NR(1, 1)); |
158 | ||
159 | return !gpio_get_value(IMX_GPIO_NR(1, 1)); | |
160 | } | |
161 | ||
3fec2c67 BT |
162 | #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ |
163 | PAD_CTL_PUS_100K_UP) | |
164 | #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ | |
165 | PAD_CTL_DSE_HIGH) | |
166 | ||
0f83b365 MV |
167 | int board_mmc_init(bd_t *bis) |
168 | { | |
3fec2c67 BT |
169 | static const iomux_v3_cfg_t sd1_pads[] = { |
170 | NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), | |
171 | NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), | |
172 | NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), | |
173 | NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), | |
174 | NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), | |
175 | NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), | |
176 | MX53_PAD_EIM_DA13__GPIO3_13, | |
177 | ||
178 | MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */ | |
179 | }; | |
180 | ||
0f83b365 MV |
181 | esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
182 | ||
3fec2c67 | 183 | imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); |
0f83b365 MV |
184 | |
185 | /* GPIO 2_31 is SD power */ | |
0f83b365 MV |
186 | gpio_direction_output(IMX_GPIO_NR(2, 31), 0); |
187 | ||
188 | return fsl_esdhc_initialize(bis, &esdhc_cfg); | |
189 | } | |
190 | #endif | |
191 | ||
502a710f MV |
192 | #ifdef CONFIG_VIDEO |
193 | static struct fb_videomode const ampire_wvga = { | |
194 | .name = "Ampire", | |
195 | .refresh = 60, | |
196 | .xres = 800, | |
197 | .yres = 480, | |
198 | .pixclock = 29851, /* picosecond (33.5 MHz) */ | |
199 | .left_margin = 89, | |
200 | .right_margin = 164, | |
201 | .upper_margin = 23, | |
202 | .lower_margin = 10, | |
203 | .hsync_len = 10, | |
204 | .vsync_len = 10, | |
205 | .sync = FB_SYNC_CLK_LAT_FALL, | |
206 | }; | |
207 | ||
208 | int board_video_skip(void) | |
209 | { | |
210 | int ret; | |
211 | ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); | |
212 | if (ret) | |
213 | printf("Ampire LCD cannot be configured: %d\n", ret); | |
214 | return ret; | |
215 | } | |
216 | #endif | |
217 | ||
3fec2c67 BT |
218 | #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ |
219 | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) | |
220 | ||
0f83b365 MV |
221 | static void setup_iomux_i2c(void) |
222 | { | |
3fec2c67 BT |
223 | static const iomux_v3_cfg_t i2c_pads[] = { |
224 | NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), | |
225 | NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), | |
226 | }; | |
227 | ||
228 | imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); | |
0f83b365 MV |
229 | } |
230 | ||
502a710f MV |
231 | static void setup_iomux_video(void) |
232 | { | |
233 | static const iomux_v3_cfg_t lcd_pads[] = { | |
234 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, | |
235 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, | |
236 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, | |
237 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, | |
238 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, | |
239 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, | |
240 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, | |
241 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, | |
242 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, | |
243 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, | |
244 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, | |
245 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, | |
246 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, | |
247 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, | |
248 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, | |
249 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, | |
250 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, | |
251 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, | |
252 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, | |
253 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, | |
254 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, | |
255 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, | |
256 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, | |
257 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, | |
258 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, | |
259 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, | |
260 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, | |
261 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1, | |
262 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2, | |
263 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3, | |
264 | MX53_PAD_EIM_A25__IPU_DI1_PIN12, | |
265 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15, | |
266 | }; | |
267 | ||
268 | imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); | |
269 | } | |
270 | ||
0f83b365 MV |
271 | static void setup_iomux_nand(void) |
272 | { | |
3fec2c67 BT |
273 | static const iomux_v3_cfg_t nand_pads[] = { |
274 | NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, | |
275 | PAD_CTL_DSE_HIGH), | |
276 | NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, | |
277 | PAD_CTL_DSE_HIGH), | |
278 | NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, | |
279 | PAD_CTL_DSE_HIGH), | |
280 | NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, | |
281 | PAD_CTL_DSE_HIGH), | |
282 | NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, | |
283 | PAD_CTL_PUS_100K_UP), | |
284 | NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, | |
285 | PAD_CTL_PUS_100K_UP), | |
286 | NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, | |
287 | PAD_CTL_DSE_HIGH), | |
288 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0, | |
289 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
290 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1, | |
291 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
292 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2, | |
293 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
294 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3, | |
295 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
296 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4, | |
297 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
298 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5, | |
299 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
300 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6, | |
301 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
302 | NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7, | |
303 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE), | |
304 | }; | |
305 | ||
306 | imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); | |
0f83b365 MV |
307 | } |
308 | ||
309 | static void m53_set_clock(void) | |
310 | { | |
311 | int ret; | |
312 | const uint32_t ref_clk = MXC_HCLK; | |
313 | const uint32_t dramclk = 400; | |
314 | uint32_t cpuclk; | |
315 | ||
3fec2c67 BT |
316 | imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, |
317 | PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); | |
318 | gpio_direction_input(IMX_GPIO_NR(4, 0)); | |
0f83b365 MV |
319 | |
320 | /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ | |
3fec2c67 | 321 | cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; |
0f83b365 MV |
322 | |
323 | ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); | |
324 | if (ret) | |
325 | printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); | |
326 | ||
327 | ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); | |
328 | if (ret) { | |
329 | printf("CPU: Switch peripheral clock to %dMHz failed\n", | |
330 | dramclk); | |
331 | } | |
332 | ||
333 | ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); | |
334 | if (ret) | |
335 | printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); | |
336 | } | |
337 | ||
338 | static void m53_set_nand(void) | |
339 | { | |
340 | u32 i; | |
341 | ||
342 | /* NAND flash is muxed on ATA pins */ | |
343 | setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); | |
344 | ||
345 | /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ | |
346 | for (i = 0x4; i < 0x94; i += 0x18) { | |
347 | clrbits_le32(WEIM_BASE_ADDR + i, | |
348 | WEIM_GCR2_MUX16_BYP_GRANT_MASK); | |
349 | } | |
350 | ||
351 | mxc_set_clock(0, 33, MXC_NFC_CLK); | |
352 | enable_nfc_clk(1); | |
353 | } | |
354 | ||
355 | int board_early_init_f(void) | |
356 | { | |
357 | setup_iomux_uart(); | |
358 | setup_iomux_fec(); | |
359 | setup_iomux_i2c(); | |
360 | setup_iomux_nand(); | |
502a710f | 361 | setup_iomux_video(); |
0f83b365 MV |
362 | |
363 | m53_set_clock(); | |
364 | ||
365 | mxc_set_sata_internal_clock(); | |
366 | ||
367 | /* NAND clock @ 33MHz */ | |
368 | m53_set_nand(); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | int board_init(void) | |
374 | { | |
375 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | int checkboard(void) | |
381 | { | |
382 | puts("Board: DENX M53EVK\n"); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | /* | |
388 | * NAND SPL | |
389 | */ | |
390 | #ifdef CONFIG_SPL_BUILD | |
391 | void spl_board_init(void) | |
392 | { | |
393 | setup_iomux_nand(); | |
394 | m53_set_clock(); | |
395 | m53_set_nand(); | |
396 | } | |
397 | ||
398 | u32 spl_boot_device(void) | |
399 | { | |
400 | return BOOT_DEVICE_NAND; | |
401 | } | |
402 | #endif |