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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / board / dhelectronics / dh_imx6 / dh_imx6_spl.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
0a333602
MV		 2/*
3 * DHCOM DH-iMX6 PDK SPL support
4 *
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
0a333602
MV		 6 */
7
d678a59d 8#include <common.h>
ab2a6e82 9#include <cpu_func.h>
691d719d 10#include <init.h>
0a333602
MV		 11#include <asm/arch/clock.h>
12#include <asm/arch/crm_regs.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-ddr.h>
16#include <asm/arch/mx6-pins.h>
17#include <asm/arch/sys_proto.h>
ab2a6e82 18#include <asm/cache.h>
0a333602
MV		 19#include <asm/gpio.h>
20#include <asm/mach-imx/boot_mode.h>
21#include <asm/mach-imx/iomux-v3.h>
22#include <asm/mach-imx/mxc_i2c.h>
23#include <asm/io.h>
506df9dc 24#include <asm/sections.h>
ab2a6e82 25#include <asm/system.h>
0a333602
MV		 26#include <errno.h>
27#include <fuse.h>
e37ac717 28#include <fsl_esdhc_imx.h>
0a333602
MV		 29#include <i2c.h>
30#include <mmc.h>
31#include <spl.h>
c05ed00a 32#include <linux/delay.h>
0a333602
MV		 33
34#define ENET_PAD_CTRL \
35 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
36 PAD_CTL_HYS)
37
38#define GPIO_PAD_CTRL \
39 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
40
41#define SPI_PAD_CTRL \
42 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST)
44
45#define UART_PAD_CTRL \
46 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48
49#define USDHC_PAD_CTRL \
50 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
51 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52
0a333602
MV		 53static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
54 .dram_sdclk_0 = 0x00020030,
55 .dram_sdclk_1 = 0x00020030,
56 .dram_cas = 0x00020030,
57 .dram_ras = 0x00020030,
58 .dram_reset = 0x00020030,
59 .dram_sdcke0 = 0x00003000,
60 .dram_sdcke1 = 0x00003000,
61 .dram_sdba2 = 0x00000000,
62 .dram_sdodt0 = 0x00003030,
63 .dram_sdodt1 = 0x00003030,
64 .dram_sdqs0 = 0x00000030,
65 .dram_sdqs1 = 0x00000030,
66 .dram_sdqs2 = 0x00000030,
67 .dram_sdqs3 = 0x00000030,
68 .dram_sdqs4 = 0x00000030,
69 .dram_sdqs5 = 0x00000030,
70 .dram_sdqs6 = 0x00000030,
71 .dram_sdqs7 = 0x00000030,
72 .dram_dqm0 = 0x00020030,
73 .dram_dqm1 = 0x00020030,
74 .dram_dqm2 = 0x00020030,
75 .dram_dqm3 = 0x00020030,
76 .dram_dqm4 = 0x00020030,
77 .dram_dqm5 = 0x00020030,
78 .dram_dqm6 = 0x00020030,
79 .dram_dqm7 = 0x00020030,
80};
81
82static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
83 .grp_ddr_type = 0x000C0000,
84 .grp_ddrmode_ctl = 0x00020000,
85 .grp_ddrpke = 0x00000000,
86 .grp_addds = 0x00000030,
87 .grp_ctlds = 0x00000030,
88 .grp_ddrmode = 0x00020000,
89 .grp_b0ds = 0x00000030,
90 .grp_b1ds = 0x00000030,
91 .grp_b2ds = 0x00000030,
92 .grp_b3ds = 0x00000030,
93 .grp_b4ds = 0x00000030,
94 .grp_b5ds = 0x00000030,
95 .grp_b6ds = 0x00000030,
96 .grp_b7ds = 0x00000030,
97};
98
99static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
100 .dram_sdclk_0 = 0x00020030,
101 .dram_sdclk_1 = 0x00020030,
102 .dram_cas = 0x00020030,
103 .dram_ras = 0x00020030,
104 .dram_reset = 0x00020030,
105 .dram_sdcke0 = 0x00003000,
106 .dram_sdcke1 = 0x00003000,
107 .dram_sdba2 = 0x00000000,
108 .dram_sdodt0 = 0x00003030,
109 .dram_sdodt1 = 0x00003030,
110 .dram_sdqs0 = 0x00000030,
111 .dram_sdqs1 = 0x00000030,
112 .dram_sdqs2 = 0x00000030,
113 .dram_sdqs3 = 0x00000030,
114 .dram_sdqs4 = 0x00000030,
115 .dram_sdqs5 = 0x00000030,
116 .dram_sdqs6 = 0x00000030,
117 .dram_sdqs7 = 0x00000030,
118 .dram_dqm0 = 0x00020030,
119 .dram_dqm1 = 0x00020030,
120 .dram_dqm2 = 0x00020030,
121 .dram_dqm3 = 0x00020030,
122 .dram_dqm4 = 0x00020030,
123 .dram_dqm5 = 0x00020030,
124 .dram_dqm6 = 0x00020030,
125 .dram_dqm7 = 0x00020030,
126};
127
128static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
129 .grp_ddr_type = 0x000C0000,
130 .grp_ddrmode_ctl = 0x00020000,
131 .grp_ddrpke = 0x00000000,
132 .grp_addds = 0x00000030,
133 .grp_ctlds = 0x00000030,
134 .grp_ddrmode = 0x00020000,
135 .grp_b0ds = 0x00000030,
136 .grp_b1ds = 0x00000030,
137 .grp_b2ds = 0x00000030,
138 .grp_b3ds = 0x00000030,
139 .grp_b4ds = 0x00000030,
140 .grp_b5ds = 0x00000030,
141 .grp_b6ds = 0x00000030,
142 .grp_b7ds = 0x00000030,
143};
144
0481bef0
LZ		 145static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
146 .p0_mpwldectrl0 = 0x00150019,
147 .p0_mpwldectrl1 = 0x001C000B,
148 .p1_mpwldectrl0 = 0x00020018,
149 .p1_mpwldectrl1 = 0x0002000C,
150 .p0_mpdgctrl0 = 0x43140320,
151 .p0_mpdgctrl1 = 0x03080304,
152 .p1_mpdgctrl0 = 0x43180320,
153 .p1_mpdgctrl1 = 0x03100254,
154 .p0_mprddlctl = 0x4830383C,
155 .p1_mprddlctl = 0x3836323E,
156 .p0_mpwrdlctl = 0x3E444642,
157 .p1_mpwrdlctl = 0x42344442,
158};
159
160static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
161 .p0_mpwldectrl0 = 0x0040003C,
162 .p0_mpwldectrl1 = 0x0032003E,
163 .p0_mpdgctrl0 = 0x42350231,
164 .p0_mpdgctrl1 = 0x021A0218,
165 .p0_mprddlctl = 0x4B4B4E49,
166 .p0_mpwrdlctl = 0x3F3F3035,
167};
168
169static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
a44ca134
LZ		 170 .p0_mpwldectrl0 = 0x001a001a,
171 .p0_mpwldectrl1 = 0x00260015,
172 .p0_mpdgctrl0 = 0x030c0320,
173 .p0_mpdgctrl1 = 0x03100304,
174 .p0_mprddlctl = 0x432e3538,
175 .p0_mpwrdlctl = 0x363f423d,
176 .p1_mpwldectrl0 = 0x0006001e,
177 .p1_mpwldectrl1 = 0x00050015,
178 .p1_mpdgctrl0 = 0x031c0324,
179 .p1_mpdgctrl1 = 0x030c0258,
180 .p1_mprddlctl = 0x3834313f,
181 .p1_mpwrdlctl = 0x47374a42,
0a333602
MV		 182};
183
0481bef0
LZ		 184static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
185 .p0_mpwldectrl0 = 0x003A003A,
186 .p0_mpwldectrl1 = 0x0030002F,
187 .p1_mpwldectrl0 = 0x002F0038,
188 .p1_mpwldectrl1 = 0x00270039,
189 .p0_mpdgctrl0 = 0x420F020F,
190 .p0_mpdgctrl1 = 0x01760175,
191 .p1_mpdgctrl0 = 0x41640171,
192 .p1_mpdgctrl1 = 0x015E0160,
193 .p0_mprddlctl = 0x45464B4A,
194 .p1_mprddlctl = 0x49484A46,
195 .p0_mpwrdlctl = 0x40402E32,
196 .p1_mpwrdlctl = 0x3A3A3231,
197};
198
199static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
200 .p0_mpwldectrl0 = 0x0040003C,
201 .p0_mpwldectrl1 = 0x0032003E,
202 .p0_mpdgctrl0 = 0x42350231,
203 .p0_mpdgctrl1 = 0x021A0218,
204 .p0_mprddlctl = 0x4B4B4E49,
205 .p0_mpwrdlctl = 0x3F3F3035,
206};
207
208/*
209 * 2 Gbit DDR3 memory
210 * - NANYA #NT5CC128M16IP-DII
211 * - NANYA #NT5CB128M16FP-DII
212 */
213static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
0a333602 214 .mem_speed = 1600,
b979e352 215 .density = 2,
0481bef0 216 .width = 16,
0a333602
MV		 217 .banks = 8,
218 .rowaddr = 14,
219 .coladdr = 10,
220 .pagesz = 2,
0481bef0 221 .trcd = 1375,
b979e352
MV		 222 .trcmin = 5863,
223 .trasmin = 3750,
0a333602
MV		 224};
225
0481bef0
LZ		 226/*
227 * 4 Gbit DDR3 memory
228 * - Intelligent Memory #IM4G16D3EABG-125I
229 */
230static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
231 .mem_speed = 1600,
232 .density = 4,
233 .width = 16,
234 .banks = 8,
235 .rowaddr = 15,
236 .coladdr = 10,
237 .pagesz = 2,
238 .trcd = 1375,
239 .trcmin = 4875,
240 .trasmin = 3500,
241};
242
243/* DDR3 64bit */
244static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
0a333602
MV		 245 /* width of data bus:0=16,1=32,2=64 */
246 .dsize = 2,
0481bef0
LZ		 247 .cs_density = 32,
248 .ncs = 1, /* single chip select */
249 .cs1_mirror = 1,
250 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
251 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
252 .walat = 1, /* Write additional latency */
253 .ralat = 5, /* Read additional latency */
254 .mif3_mode = 3, /* Command prediction working mode */
255 .bi_on = 1, /* Bank interleaving enabled */
256 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
257 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
258 .refsel = 1, /* Refresh cycles at 32KHz */
259 .refr = 3, /* 4 refresh commands per refresh cycle */
260};
261
262/* DDR3 32bit */
263static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
264 /* width of data bus:0=16,1=32,2=64 */
265 .dsize = 1,
266 .cs_density = 32,
0a333602 267 .ncs = 1, /* single chip select */
b979e352 268 .cs1_mirror = 1,
0a333602
MV		 269 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
270 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
271 .walat = 1, /* Write additional latency */
272 .ralat = 5, /* Read additional latency */
273 .mif3_mode = 3, /* Command prediction working mode */
274 .bi_on = 1, /* Bank interleaving enabled */
275 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
276 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
b979e352
MV		 277 .refsel = 1, /* Refresh cycles at 32KHz */
278 .refr = 3, /* 4 refresh commands per refresh cycle */
0a333602
MV		 279};
280
281static void ccgr_init(void)
282{
283 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
284
285 writel(0x00C03F3F, &ccm->CCGR0);
286 writel(0x0030FC03, &ccm->CCGR1);
287 writel(0x0FFFC000, &ccm->CCGR2);
288 writel(0x3FF00000, &ccm->CCGR3);
289 writel(0x00FFF300, &ccm->CCGR4);
290 writel(0x0F0000C3, &ccm->CCGR5);
291 writel(0x000003FF, &ccm->CCGR6);
292}
293
294/* Board ID */
295static iomux_v3_cfg_t const hwcode_pads[] = {
296 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
297 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
298 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
299};
300
301static void setup_iomux_boardid(void)
302{
303 /* HW code pins: Setup alternate function and configure pads */
304 SETUP_IOMUX_PADS(hwcode_pads);
305}
306
659ca2dd
LZ		 307/* DDR Code */
308static iomux_v3_cfg_t const ddrcode_pads[] = {
309 IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
310 IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
311};
312
313static void setup_iomux_ddrcode(void)
314{
315 /* ddr code pins */
316 SETUP_IOMUX_PADS(ddrcode_pads);
317}
318
319enum dhcom_ddr3_code {
320 DH_DDR3_SIZE_256MIB = 0x00,
321 DH_DDR3_SIZE_512MIB = 0x01,
322 DH_DDR3_SIZE_1GIB = 0x02,
323 DH_DDR3_SIZE_2GIB = 0x03
324};
325
326#define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
327#define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
328
329enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
330{
331 enum dhcom_ddr3_code ddr3_code;
332
333 gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
334 gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
335
336 gpio_direction_input(DDR3_CODE_BIT_0);
337 gpio_direction_input(DDR3_CODE_BIT_1);
338
339 /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
340 ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
341 | (!!gpio_get_value(DDR3_CODE_BIT_0));
342
343 return ddr3_code;
344}
345
0a333602
MV		 346/* GPIO */
347static iomux_v3_cfg_t const gpio_pads[] = {
348 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
349 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
350 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
351 IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
352 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
353 IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
354 IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
355 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
356 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
357 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
358 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
359 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
360 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
361 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
362 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
363 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
364 IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
365 IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
366 IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
367 IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
368 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
369 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
370 IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
371};
372
373static void setup_iomux_gpio(void)
374{
375 SETUP_IOMUX_PADS(gpio_pads);
376}
377
378/* Ethernet */
379static iomux_v3_cfg_t const enet_pads[] = {
380 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
381 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
382 IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
383 IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
384 IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
385 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
386 IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
387 IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
388 IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
389 IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
390 /* SMSC PHY Reset */
391 IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
392 /* ENET_VIO_GPIO */
393 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
394 /* ENET_Interrupt - (not used) */
395 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
396};
397
398static void setup_iomux_enet(void)
399{
400 SETUP_IOMUX_PADS(enet_pads);
401}
402
403/* SD interface */
404static iomux_v3_cfg_t const usdhc2_pads[] = {
405 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
406 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
407 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
408 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
409 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
410 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
411 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
412};
413
414/* onboard microSD */
415static iomux_v3_cfg_t const usdhc3_pads[] = {
416 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
417 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
418 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
419 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
420 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
421 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
422 IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
423};
424
425/* eMMC */
426static iomux_v3_cfg_t const usdhc4_pads[] = {
427 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
428 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
429 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
430 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
431 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
432 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
433 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
434 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
435 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
436 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
437};
438
439/* SD */
440static void setup_iomux_sd(void)
441{
442 SETUP_IOMUX_PADS(usdhc2_pads);
443 SETUP_IOMUX_PADS(usdhc3_pads);
444 SETUP_IOMUX_PADS(usdhc4_pads);
445}
446
447/* SPI */
448static iomux_v3_cfg_t const ecspi1_pads[] = {
6e75cb23
LZ		 449 /* SS0 - SS of boot flash */
450 IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 |
451 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
452 /* SS2 - SS of DHCOM SPI1 */
453 IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 |
454 MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
455
0a333602
MV		 456 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
457 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
458 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
459};
460
461static void setup_iomux_spi(void)
462{
463 SETUP_IOMUX_PADS(ecspi1_pads);
464}
465
466int board_spi_cs_gpio(unsigned bus, unsigned cs)
467{
468 if (bus == 0 && cs == 0)
469 return IMX_GPIO_NR(2, 30);
470 else
471 return -1;
472}
473
474/* UART */
475static iomux_v3_cfg_t const uart1_pads[] = {
476 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
477 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
478};
479
480static void setup_iomux_uart(void)
481{
482 SETUP_IOMUX_PADS(uart1_pads);
483}
484
5c47bf71
CH		 485#ifdef CONFIG_FSL_USDHC
486struct fsl_esdhc_cfg usdhc_cfg[1] = {
487 {USDHC4_BASE_ADDR},
488};
489
490int board_mmc_get_env_dev(int devno)
491{
492 return devno - 1;
493}
494
495int board_mmc_getcd(struct mmc *mmc)
496{
497 return 1; /* eMMC/uSDHC4 is always present */
498}
499
b75d8dc5 500int board_mmc_init(struct bd_info *bis)
5c47bf71
CH		 501{
502 SETUP_IOMUX_PADS(usdhc4_pads);
503 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
504 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
505 usdhc_cfg[0].max_bus_width = 8;
506
507 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
508}
509#endif
510
0a333602
MV		 511/* USB */
512static iomux_v3_cfg_t const usb_pads[] = {
513 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
514 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
515};
516
517static void setup_iomux_usb(void)
518{
519 SETUP_IOMUX_PADS(usb_pads);
520}
521
aa345056
LZ		 522/* Perform DDR DRAM calibration */
523static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
524{
525 int ret = 0;
526
527#ifdef CONFIG_MX6_DDRCAL
528 udelay(100);
529 ret = mmdc_do_write_level_calibration(sysinfo);
530 if (ret) {
531 printf("DDR3: Write level calibration error [%d]\n", ret);
532 return ret;
533 }
534
535 ret = mmdc_do_dqs_calibration(sysinfo);
536 if (ret) {
537 printf("DDR3: DQS calibration error [%d]\n", ret);
538 return ret;
539 }
540#endif /* CONFIG_MX6_DDRCAL */
541
542 return ret;
543}
544
0481bef0
LZ		 545
546/* DRAM */
547static void dhcom_spl_dram_init(void)
548{
549 enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
550
551 if (is_mx6dq()) {
552 mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
553 &dhcom6dq_grp_ioregs);
554 switch (ddr3_code) {
555 default:
556 printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
557 printf(" choosing 1024 MB\n");
558 /* fall through */
559 case DH_DDR3_SIZE_1GIB:
560 mx6_dram_cfg(&dhcom_ddr_64bit,
561 &dhcom_mmdc_calib_4x2g_1066,
562 &dhcom_mem_ddr_2g);
563 break;
564 case DH_DDR3_SIZE_2GIB:
565 mx6_dram_cfg(&dhcom_ddr_64bit,
566 &dhcom_mmdc_calib_4x4g_1066,
567 &dhcom_mem_ddr_4g);
568 break;
569 }
570
571 /* Perform DDR DRAM calibration */
aa345056 572 spl_dram_perform_cal(&dhcom_ddr_64bit);
0481bef0
LZ		 573
574 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
575 mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
576 &dhcom6sdl_grp_ioregs);
577 switch (ddr3_code) {
578 default:
579 printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
580 printf(" choosing 1024 MB\n");
581 /* fall through */
582 case DH_DDR3_SIZE_1GIB:
583 mx6_dram_cfg(&dhcom_ddr_64bit,
584 &dhcom_mmdc_calib_4x2g_800,
585 &dhcom_mem_ddr_2g);
586 break;
587 }
588
589 /* Perform DDR DRAM calibration */
aa345056 590 spl_dram_perform_cal(&dhcom_ddr_64bit);
0481bef0
LZ		 591
592 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
593 mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
594 &dhcom6sdl_grp_ioregs);
595 switch (ddr3_code) {
596 default:
597 printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
598 printf(" choosing 512 MB\n");
599 /* fall through */
600 case DH_DDR3_SIZE_512MIB:
601 mx6_dram_cfg(&dhcom_ddr_32bit,
602 &dhcom_mmdc_calib_2x2g_800,
603 &dhcom_mem_ddr_2g);
604 break;
605 case DH_DDR3_SIZE_1GIB:
606 mx6_dram_cfg(&dhcom_ddr_32bit,
607 &dhcom_mmdc_calib_2x4g_800,
608 &dhcom_mem_ddr_4g);
609 break;
610 }
611
612 /* Perform DDR DRAM calibration */
aa345056 613 spl_dram_perform_cal(&dhcom_ddr_32bit);
0481bef0
LZ		 614 }
615}
616
ab2a6e82
MV		 617void dram_bank_mmu_setup(int bank)
618{
619 int i;
620
621 set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
622 set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
623
624 for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
625 i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +
626 (SZ_1G >> MMU_SECTION_SHIFT));
627 i++)
628 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
629}
630
0a333602
MV		 631void board_init_f(ulong dummy)
632{
633 /* setup AIPS and disable watchdog */
634 arch_cpu_init();
635
636 ccgr_init();
637 gpr_init();
638
639 /* setup GP timer */
640 timer_init();
641
642 setup_iomux_boardid();
659ca2dd 643 setup_iomux_ddrcode();
0a333602
MV		 644 setup_iomux_gpio();
645 setup_iomux_enet();
646 setup_iomux_sd();
647 setup_iomux_spi();
648 setup_iomux_uart();
649 setup_iomux_usb();
650
651 /* UART clocks enabled and gd valid - init serial console */
652 preloader_console_init();
653
0481bef0
LZ		 654 /* DDR3 initialization */
655 dhcom_spl_dram_init();
3d81584d 656
ab2a6e82
MV		 657 /* Set up early MMU tables at the beginning of DRAM and start d-cache */
658 gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
659 gd->arch.tlb_size = PGTABLE_SIZE;
660 enable_caches();
661
0a333602
MV		 662 /* Clear the BSS. */
663 memset(__bss_start, 0, __bss_end - __bss_start);
664
665 /* load/boot image from boot device */
666 board_init_r(NULL, 0);
667}
ab2a6e82
MV		 668
669void spl_board_prepare_for_boot(void)
670{
671 /*
672 * Flush and disable dcache. Without it, the following bootstage might fail randomly because
673 * dirty cache lines may not have been written back to DRAM.
674 *
675 * If dcache_disable() would be omitted, the following scenario may occur:
676 *
677 * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled
678 * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations
679 * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old
680 * state of the content.
681 *
682 * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was
683 * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data.
684 */
685 dcache_disable(); /* implies flush_dcache_all() */
686}
"Das U-Boot" Source Tree