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1 | /* |
2 | * (C) Copyright 2000-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <mpc824x.h> | |
29 | #include <asm/processor.h> | |
30 | #include <asm/io.h> | |
31 | #include <pci.h> | |
32 | #include <ide.h> | |
10efa024 | 33 | #include <netdev.h> |
80885a9d WD |
34 | #include "piix_pci.h" |
35 | #include "eXalion.h" | |
36 | ||
37 | int checkboard (void) | |
38 | { | |
39 | ulong busfreq = get_bus_freq (0); | |
40 | char buf[32]; | |
41 | ||
42 | printf ("Board: eXalion MPC824x - CHRP (MAP B)\n"); | |
43 | printf ("Built: %s at %s\n", __DATE__, __TIME__); | |
44 | printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); | |
45 | ||
46 | return 0; | |
47 | } | |
48 | ||
49 | int checkflash (void) | |
50 | { | |
51 | printf ("checkflash\n"); | |
52 | flash_init (); | |
53 | return (0); | |
54 | } | |
55 | ||
9973e3c6 | 56 | phys_size_t initdram (int board_type) |
80885a9d WD |
57 | { |
58 | int i, cnt; | |
6d0f6bcf | 59 | volatile uchar *base = CONFIG_SYS_SDRAM_BASE; |
80885a9d WD |
60 | volatile ulong *addr; |
61 | ulong save[32]; | |
62 | ulong val, ret = 0; | |
63 | ||
6d0f6bcf | 64 | for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; |
80885a9d WD |
65 | cnt >>= 1) { |
66 | addr = (volatile ulong *) base + cnt; | |
67 | save[i++] = *addr; | |
68 | *addr = ~cnt; | |
69 | } | |
70 | ||
71 | addr = (volatile ulong *) base; | |
72 | save[i] = *addr; | |
73 | *addr = 0; | |
74 | ||
75 | if (*addr != 0) { | |
76 | *addr = save[i]; | |
77 | goto Done; | |
78 | } | |
79 | ||
6d0f6bcf | 80 | for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { |
80885a9d WD |
81 | addr = (volatile ulong *) base + cnt; |
82 | val = *addr; | |
83 | *addr = save[--i]; | |
84 | if (val != ~cnt) { | |
85 | ulong new_bank0_end = cnt * sizeof (long) - 1; | |
86 | ulong mear1 = mpc824x_mpc107_getreg (MEAR1); | |
87 | ulong emear1 = mpc824x_mpc107_getreg (EMEAR1); | |
88 | ||
89 | mear1 = (mear1 & 0xFFFFFF00) | | |
90 | ((new_bank0_end & MICR_ADDR_MASK) >> | |
91 | MICR_ADDR_SHIFT); | |
92 | emear1 = (emear1 & 0xFFFFFF00) | | |
93 | ((new_bank0_end & MICR_ADDR_MASK) >> | |
94 | MICR_EADDR_SHIFT); | |
95 | mpc824x_mpc107_setreg (MEAR1, mear1); | |
96 | mpc824x_mpc107_setreg (EMEAR1, emear1); | |
97 | ||
98 | ret = cnt * sizeof (long); | |
99 | goto Done; | |
100 | } | |
101 | } | |
102 | ||
6d0f6bcf | 103 | ret = CONFIG_SYS_MAX_RAM_SIZE; |
80885a9d WD |
104 | Done: |
105 | return ret; | |
106 | } | |
107 | ||
108 | int misc_init_r (void) | |
109 | { | |
110 | pci_dev_t bdf; | |
111 | u32 val32; | |
112 | u8 val8; | |
113 | ||
114 | puts ("ISA: "); | |
115 | bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0); | |
116 | if (bdf == -1) { | |
117 | puts ("Unable to find PIIX4 ISA bridge !\n"); | |
118 | hang (); | |
119 | } | |
120 | ||
121 | /* set device for normal ISA instead EIO */ | |
122 | pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32); | |
123 | val32 |= 0x00000001; | |
124 | pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32); | |
125 | printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf), | |
126 | PCI_DEV (bdf), PCI_FUNC (bdf)); | |
127 | ||
128 | puts ("ISA: "); | |
129 | bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0); | |
130 | if (bdf == -1) { | |
131 | puts ("Unable to find PIIX4 IDE controller !\n"); | |
132 | hang (); | |
133 | } | |
134 | ||
135 | /* Init BMIBA register */ | |
136 | /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */ | |
137 | /* val32 |= 0x1000; */ | |
138 | /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */ | |
139 | ||
140 | /* Enable BUS master and IO access */ | |
141 | val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO; | |
142 | pci_write_config_dword (bdf, PCI_COMMAND, val32); | |
143 | ||
144 | /* Set latency */ | |
145 | pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8); | |
146 | val8 = 0x40; | |
147 | pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8); | |
148 | ||
149 | /* Enable Primary ATA/IDE */ | |
150 | pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32); | |
151 | /* val32 = 0xa307a307; */ | |
152 | val32 = 0x00008000; | |
153 | pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32); | |
154 | ||
155 | ||
156 | printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf), | |
157 | PCI_DEV (bdf), PCI_FUNC (bdf)); | |
158 | ||
159 | /* Try to get FAT working... */ | |
160 | /* fat_register_read(ide_read); */ | |
161 | ||
162 | ||
163 | return (0); | |
164 | } | |
165 | ||
166 | /* | |
167 | * Show/Init PCI devices on the specified bus number. | |
168 | */ | |
169 | ||
170 | void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev) | |
171 | { | |
172 | unsigned char line; | |
173 | ||
174 | switch (PCI_DEV (dev)) { | |
175 | case 16: | |
176 | line = PCI_INT_A; | |
177 | break; | |
178 | case 17: | |
179 | line = PCI_INT_B; | |
180 | break; | |
181 | case 18: | |
182 | line = PCI_INT_C; | |
183 | break; | |
184 | case 19: | |
185 | line = PCI_INT_D; | |
186 | break; | |
187 | #if defined (CONFIG_MPC8245) | |
188 | case 20: | |
189 | line = PCI_INT_A; | |
190 | break; | |
191 | case 21: | |
192 | line = PCI_INT_B; | |
193 | break; | |
194 | case 22: | |
195 | line = PCI_INT_NA; | |
196 | break; | |
197 | #endif | |
198 | default: | |
199 | line = PCI_INT_A; | |
200 | break; | |
201 | } | |
202 | pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line); | |
203 | } | |
204 | ||
205 | ||
206 | /* | |
207 | * Initialize PCI Devices, report devices found. | |
208 | */ | |
209 | #ifndef CONFIG_PCI_PNP | |
210 | #if defined (CONFIG_MPC8240) | |
211 | static struct pci_config_table pci_eXalion_config_table[] = { | |
212 | { | |
213 | /* Intel 82559ER ethernet controller */ | |
214 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, | |
215 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, | |
216 | PCI_ENET0_MEMADDR, | |
217 | PCI_COMMAND_MEMORY | | |
218 | PCI_COMMAND_MASTER}}, | |
219 | { | |
220 | /* Intel 82371AB PIIX4 PCI to ISA bridge */ | |
221 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, | |
222 | pci_cfgfunc_config_device, {0, | |
223 | 0, | |
224 | PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, | |
225 | { | |
226 | /* Intel 82371AB PIIX4 IDE controller */ | |
227 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01, | |
228 | pci_cfgfunc_config_device, {0, | |
229 | 0, | |
230 | PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, | |
231 | {} | |
232 | }; | |
233 | #elif defined (CONFIG_MPC8245) | |
234 | static struct pci_config_table pci_eXalion_config_table[] = { | |
235 | { | |
236 | /* Intel 82559ER ethernet controller */ | |
237 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00, | |
238 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, | |
239 | PCI_ENET0_MEMADDR, | |
240 | PCI_COMMAND_MEMORY | | |
241 | PCI_COMMAND_MASTER}}, | |
242 | { | |
243 | /* Intel 82559ER ethernet controller */ | |
244 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, | |
245 | pci_cfgfunc_config_device, {PCI_ENET1_IOADDR, | |
246 | PCI_ENET1_MEMADDR, | |
247 | PCI_COMMAND_MEMORY | | |
248 | PCI_COMMAND_MASTER}}, | |
249 | { | |
250 | /* Broadcom BCM5690 Gigabit switch */ | |
251 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, | |
252 | pci_cfgfunc_config_device, {PCI_ENET2_IOADDR, | |
253 | PCI_ENET2_MEMADDR, | |
254 | PCI_COMMAND_MEMORY | | |
255 | PCI_COMMAND_MASTER}}, | |
256 | { | |
257 | /* Broadcom BCM5690 Gigabit switch */ | |
258 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00, | |
259 | pci_cfgfunc_config_device, {PCI_ENET3_IOADDR, | |
260 | PCI_ENET3_MEMADDR, | |
261 | PCI_COMMAND_MEMORY | | |
262 | PCI_COMMAND_MASTER}}, | |
263 | { | |
264 | /* Intel 82371AB PIIX4 PCI to ISA bridge */ | |
265 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00, | |
266 | pci_cfgfunc_config_device, {0, | |
267 | 0, | |
268 | PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, | |
269 | { | |
270 | /* Intel 82371AB PIIX4 IDE controller */ | |
271 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01, | |
272 | pci_cfgfunc_config_device, {0, | |
273 | 0, | |
274 | PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, | |
275 | {} | |
276 | }; | |
277 | #else | |
278 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
279 | #endif | |
280 | ||
281 | #endif /* #ifndef CONFIG_PCI_PNP */ | |
282 | ||
283 | struct pci_controller hose = { | |
284 | #ifndef CONFIG_PCI_PNP | |
285 | config_table:pci_eXalion_config_table, | |
286 | fixup_irq:pci_eXalion_fixup_irq, | |
287 | #endif | |
288 | }; | |
289 | ||
290 | void pci_init_board (void) | |
291 | { | |
292 | pci_mpc824x_init (&hose); | |
293 | } | |
10efa024 BW |
294 | |
295 | int board_eth_init(bd_t *bis) | |
296 | { | |
297 | return pci_eth_init(bis); | |
298 | } |