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7ebf7443 WD |
1 | /* |
2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
3 | * Andreas Heppel <aheppel@sysgo.de> | |
4 | * (C) Copyright 2001 ELTEC Elektronik AG | |
5 | * Frank Gottschling <fgottschling@eltec.de> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <command.h> | |
28 | #include <mpc106.h> | |
29 | #include <mk48t59.h> | |
30 | #include <74xx_7xx.h> | |
31 | #include <ns87308.h> | |
32 | #include <video_fb.h> | |
8ca0b3f9 | 33 | #include <netdev.h> |
7ebf7443 | 34 | |
d87080b7 WD |
35 | DECLARE_GLOBAL_DATA_PTR; |
36 | ||
7ebf7443 WD |
37 | /*---------------------------------------------------------------------------*/ |
38 | /* | |
39 | * Get Bus clock frequency | |
40 | */ | |
41 | ulong bab7xx_get_bus_freq (void) | |
42 | { | |
bf9e3b38 WD |
43 | /* |
44 | * The GPIO Port 1 on BAB7xx reflects the bus speed. | |
45 | */ | |
46 | volatile struct GPIO *gpio = | |
6d0f6bcf | 47 | (struct GPIO *) (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_GPIO_BASE); |
7ebf7443 | 48 | |
bf9e3b38 | 49 | unsigned char data = gpio->dta1; |
7ebf7443 | 50 | |
bf9e3b38 WD |
51 | if (data & 0x02) |
52 | return 66666666; | |
7ebf7443 | 53 | |
bf9e3b38 | 54 | return 83333333; |
7ebf7443 WD |
55 | } |
56 | ||
57 | /*---------------------------------------------------------------------------*/ | |
58 | ||
59 | /* | |
60 | * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz) | |
61 | */ | |
62 | ulong bab7xx_get_gclk_freq (void) | |
63 | { | |
bf9e3b38 WD |
64 | static const int pllratio_to_factor[] = { |
65 | 00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, | |
66 | 00, | |
67 | }; | |
7ebf7443 | 68 | |
bf9e3b38 WD |
69 | return pllratio_to_factor[get_hid1 () >> 28] * |
70 | (bab7xx_get_bus_freq () / 10); | |
7ebf7443 WD |
71 | } |
72 | ||
73 | /*----------------------------------------------------------------------------*/ | |
74 | ||
75 | int checkcpu (void) | |
76 | { | |
bf9e3b38 | 77 | uint pvr = get_pvr (); |
7ebf7443 | 78 | |
bf9e3b38 WD |
79 | printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF); |
80 | printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000, | |
81 | bab7xx_get_bus_freq () / 1000000); | |
7ebf7443 | 82 | |
bf9e3b38 | 83 | return (0); |
7ebf7443 WD |
84 | } |
85 | ||
86 | /* ------------------------------------------------------------------------- */ | |
87 | ||
88 | int checkboard (void) | |
89 | { | |
6d0f6bcf | 90 | #ifdef CONFIG_SYS_ADDRESS_MAP_A |
bf9e3b38 | 91 | puts ("Board: ELTEC BAB7xx PReP\n"); |
7ebf7443 | 92 | #else |
bf9e3b38 | 93 | puts ("Board: ELTEC BAB7xx CHRP\n"); |
7ebf7443 | 94 | #endif |
bf9e3b38 | 95 | return (0); |
7ebf7443 WD |
96 | } |
97 | ||
98 | /* ------------------------------------------------------------------------- */ | |
99 | ||
100 | int checkflash (void) | |
101 | { | |
bf9e3b38 WD |
102 | /* TODO: XXX XXX XXX */ |
103 | printf ("2 MB ## Test not implemented yet ##\n"); | |
104 | return (0); | |
7ebf7443 WD |
105 | } |
106 | ||
107 | /* ------------------------------------------------------------------------- */ | |
108 | ||
109 | ||
110 | static unsigned int mpc106_read_cfg_dword (unsigned int reg) | |
111 | { | |
bf9e3b38 | 112 | unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); |
7ebf7443 | 113 | |
bf9e3b38 | 114 | out32r (MPC106_REG_ADDR, reg_addr); |
7ebf7443 | 115 | |
bf9e3b38 | 116 | return (in32r (MPC106_REG_DATA | (reg & 0x3))); |
7ebf7443 WD |
117 | } |
118 | ||
119 | /* ------------------------------------------------------------------------- */ | |
120 | ||
121 | long int dram_size (int board_type) | |
122 | { | |
bf9e3b38 WD |
123 | /* No actual initialisation to do - done when setting up |
124 | * PICRs MCCRs ME/SARs etc in ram_init.S. | |
125 | */ | |
7ebf7443 | 126 | |
bf9e3b38 | 127 | register unsigned long i, msar1, mear1, memSize; |
7ebf7443 | 128 | |
6d0f6bcf | 129 | #if defined(CONFIG_SYS_MEMTEST) |
bf9e3b38 | 130 | register unsigned long reg; |
7ebf7443 | 131 | |
bf9e3b38 | 132 | printf ("Testing DRAM\n"); |
7ebf7443 | 133 | |
bf9e3b38 | 134 | /* write each mem addr with it's address */ |
6d0f6bcf | 135 | for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) |
bf9e3b38 | 136 | *reg = reg; |
7ebf7443 | 137 | |
6d0f6bcf | 138 | for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) { |
bf9e3b38 WD |
139 | if (*reg != reg) |
140 | return -1; | |
141 | } | |
7ebf7443 WD |
142 | #endif |
143 | ||
bf9e3b38 WD |
144 | /* |
145 | * Since MPC106 memory controller chip has already been set to | |
146 | * control all memory, just read and interpret its memory boundery register. | |
147 | */ | |
148 | memSize = 0; | |
149 | msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); | |
150 | mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); | |
151 | i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; | |
152 | ||
153 | do { | |
154 | if (i & 0x01) /* is bank enabled ? */ | |
155 | memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; | |
156 | msar1 >>= 8; | |
157 | mear1 >>= 8; | |
158 | i >>= 1; | |
159 | } while (i); | |
160 | ||
161 | return (memSize * 0x100000); | |
7ebf7443 WD |
162 | } |
163 | ||
164 | /* ------------------------------------------------------------------------- */ | |
165 | ||
9973e3c6 | 166 | phys_size_t initdram (int board_type) |
7ebf7443 | 167 | { |
bf9e3b38 | 168 | return dram_size (board_type); |
7ebf7443 WD |
169 | } |
170 | ||
171 | /* ------------------------------------------------------------------------- */ | |
172 | ||
173 | void after_reloc (ulong dest_addr) | |
174 | { | |
bf9e3b38 WD |
175 | /* |
176 | * Jump to the main U-Boot board init code | |
177 | */ | |
178 | board_init_r ((gd_t *) gd, dest_addr); | |
7ebf7443 WD |
179 | } |
180 | ||
181 | /* ------------------------------------------------------------------------- */ | |
182 | ||
183 | /* | |
184 | * do_reset is done here because in this case it is board specific, since the | |
185 | * 7xx CPUs can only be reset by external HW (the RTC in this case). | |
186 | */ | |
bf9e3b38 | 187 | void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) |
7ebf7443 WD |
188 | { |
189 | #if defined(CONFIG_RTC_MK48T59) | |
bf9e3b38 WD |
190 | /* trigger watchdog immediately */ |
191 | rtc_set_watchdog (1, RTC_WD_RB_16TH); | |
7ebf7443 | 192 | #else |
bf9e3b38 | 193 | #error "You must define the macro CONFIG_RTC_MK48T59." |
7ebf7443 WD |
194 | #endif |
195 | } | |
196 | ||
197 | /* ------------------------------------------------------------------------- */ | |
198 | ||
199 | #if defined(CONFIG_WATCHDOG) | |
200 | /* | |
201 | * Since the 7xx CPUs don't have an internal watchdog, this function is | |
202 | * board specific. We use the RTC here. | |
203 | */ | |
bf9e3b38 | 204 | void watchdog_reset (void) |
7ebf7443 WD |
205 | { |
206 | #if defined(CONFIG_RTC_MK48T59) | |
bf9e3b38 WD |
207 | /* we use a 32 sec watchdog timer */ |
208 | rtc_set_watchdog (8, RTC_WD_RB_4); | |
7ebf7443 | 209 | #else |
bf9e3b38 | 210 | #error "You must define the macro CONFIG_RTC_MK48T59." |
7ebf7443 WD |
211 | #endif |
212 | } | |
bf9e3b38 | 213 | #endif /* CONFIG_WATCHDOG */ |
7ebf7443 WD |
214 | |
215 | /* ------------------------------------------------------------------------- */ | |
216 | ||
217 | #ifdef CONFIG_CONSOLE_EXTRA_INFO | |
218 | extern GraphicDevice smi; | |
219 | ||
220 | void video_get_info_str (int line_number, char *info) | |
221 | { | |
bf9e3b38 WD |
222 | /* init video info strings for graphic console */ |
223 | switch (line_number) { | |
224 | case 1: | |
225 | sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz", | |
226 | (get_pvr () >> 8) & 0xFF, | |
227 | get_pvr () & 0xFF, | |
228 | bab7xx_get_gclk_freq () / 1000000, | |
229 | bab7xx_get_bus_freq () / 1000000); | |
230 | return; | |
231 | case 2: | |
232 | sprintf (info, | |
233 | " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH", | |
234 | dram_size (0) / 0x100000, flash_init () / 0x100000); | |
235 | return; | |
236 | case 3: | |
237 | sprintf (info, " %s", smi.modeIdent); | |
238 | return; | |
239 | } | |
240 | ||
241 | /* no more info lines */ | |
242 | *info = 0; | |
8bde7f77 | 243 | return; |
7ebf7443 WD |
244 | } |
245 | #endif | |
246 | ||
247 | /*---------------------------------------------------------------------------*/ | |
8ca0b3f9 BW |
248 | |
249 | int board_eth_init(bd_t *bis) | |
250 | { | |
251 | return pci_eth_init(bis); | |
252 | } |