[people/ms/u-boot.git] / board / emk / top5200 / top5200.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2003
 * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

/*****************************************************************************
 * initialize SDRAM/DDRAM controller.
 * TBD: get data from I2C EEPROM
 *****************************************************************************/
phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
#if 0
	ulong	t;
	ulong	tap_del;
#endif

	#define	MODE_EN		0x80000000
	#define	SOFT_PRE	2
	#define	SOFT_REF	4

	/* configure SDRAM start/end */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
#ifdef CONFIG_SYS_DRAM_DDR
	/* set extended mode register */
	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
#endif
	/* set mode register */
	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
	/* set mode register */
	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
	/* write default TAP delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;

#if 0
	for (tap_del = 0; tap_del < 32; tap_del++)
	{
		*(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;

		printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
		for (t = 0; t < 0x04000000; t+=4)
			*(vu_long *) t = t;
		printf ("Checking DRAM...\n");
		for (t = 0; t < 0x04000000; t+=4)
		{
			ulong	rval = *(vu_long *) t;
			if (rval != t)
			{
				printf ("mismatch at %x: ", t);
				printf (" 1.read %x", rval);
				printf (" 2.read %x", *(vu_long *) t);
				printf (" 3.read %x", *(vu_long *) t);
				break;
			}
		}
	}
#endif
#endif /* CONFIG_SYS_RAMBOOT */

	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);

	/* return total ram size */
	return dramsize;
}

/*****************************************************************************
 * print board identification
 *****************************************************************************/
int checkboard (void)
{
#if defined (CONFIG_EVAL5200)
	puts ("Board: EMK TOP5200 on EVAL5200\n");
#else
#if defined (CONFIG_LITE5200)
	puts ("Board: LITE5200\n");
#else
#if defined (CONFIG_MINI5200)
	puts ("Board: EMK TOP5200 on MINI5200\n");
#else
	puts ("Board: EMK TOP5200\n");
#endif
#endif
#endif
	return 0;
}

/*****************************************************************************
 * prepare for FLASH detection
 *****************************************************************************/
void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}

/*****************************************************************************
 * finalize FLASH setup
 *****************************************************************************/
void flash_afterinit(uint bank, ulong start, ulong size)
{
	if (bank == 0) { /* adjust mapping */
		*(vu_long *)MPC5XXX_BOOTCS_START =
		*(vu_long *)MPC5XXX_CS0_START =	START_REG(start);
		*(vu_long *)MPC5XXX_BOOTCS_STOP =
		*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
	}
}

/*****************************************************************************
 * otherinits after RAM is there and we are relocated to RAM
 * note: though this is an int function, nobody cares for the result!
 *****************************************************************************/
int misc_init_r (void)
{
#if !defined (CONFIG_LITE5200)
	/* read 'factory' part of EEPROM */
	extern void read_factory_r (void);
	read_factory_r ();
#endif
	return (0);
}

/*****************************************************************************
 * initialize the PCI system
 *****************************************************************************/
#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

/*****************************************************************************
 * provide the IDE Reset Function
 *****************************************************************************/
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
	}
}
#endif
Commit	Line	Data
c1896004 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2003
	6	* Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
	29	#include <pci.h>
	30
	31	/*****************************************************************************
	32	* initialize SDRAM/DDRAM controller.
	33	* TBD: get data from I2C EEPROM
	34	*****************************************************************************/
9973e3c6	35	phys_size_t initdram (int board_type)
c1896004 WD	36	{
c1896004 WD	37	ulong dramsize = 0;
6d0f6bcf	38	#ifndef CONFIG_SYS_RAMBOOT
d4ca31c4	39	#if 0
c1896004 WD	40	ulong t;
c1896004 WD	41	ulong tap_del;
d4ca31c4	42	#endif
c1896004 WD	43
	44	#define MODE_EN 0x80000000
	45	#define SOFT_PRE 2
	46	#define SOFT_REF 4
	47
	48	/* configure SDRAM start/end */
6d0f6bcf	49	(vu_long )MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) \| CONFIG_SYS_DRAM_RAM_SIZE;
c1896004 WD	50	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
	51
	52	/* setup config registers */
6d0f6bcf JCPV	53	(vu_long )MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
6d0f6bcf JCPV	54	(vu_long )MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
c1896004 WD	55
c1896004 WD	56	/* unlock mode register */
6d0f6bcf	57	(vu_long )MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL \| MODE_EN;
c1896004	58	/* precharge all banks */
6d0f6bcf JCPV	59	(vu_long )MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL \| MODE_EN \| SOFT_PRE;
6d0f6bcf JCPV	60	#ifdef CONFIG_SYS_DRAM_DDR
c1896004	61	/* set extended mode register */
6d0f6bcf	62	(vu_short )MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
c1896004 WD	63	#endif
c1896004 WD	64	/* set mode register */
6d0f6bcf	65	(vu_short )MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE \| 0x0400;
c1896004	66	/* precharge all banks */
6d0f6bcf	67	(vu_long )MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL \| MODE_EN \| SOFT_PRE;
c1896004	68	/* auto refresh */
6d0f6bcf	69	(vu_long )MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL \| MODE_EN \| SOFT_REF;
c1896004	70	/* set mode register */
6d0f6bcf	71	(vu_short )MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
c1896004	72	/* normal operation */
6d0f6bcf	73	(vu_long )MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
c1896004	74	/* write default TAP delay */
6d0f6bcf	75	(vu_long )MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
c1896004 WD	76
c1896004 WD	77	#if 0
d4ca31c4 WD	78	for (tap_del = 0; tap_del < 32; tap_del++)
d4ca31c4 WD	79	{
c1896004 WD	80	(vu_long )MPC5XXX_CDM_PORCFG = tap_del << 24;
	81
	82	printf ("\nTAP Delay:%x Filling DRAM...", (vu_long )MPC5XXX_CDM_PORCFG);
	83	for (t = 0; t < 0x04000000; t+=4)
	84	(vu_long ) t = t;
	85	printf ("Checking DRAM...\n");
d4ca31c4 WD	86	for (t = 0; t < 0x04000000; t+=4)
d4ca31c4 WD	87	{
c1896004	88	ulong rval = (vu_long ) t;
d4ca31c4 WD	89	if (rval != t)
d4ca31c4 WD	90	{
c1896004 WD	91	printf ("mismatch at %x: ", t);
	92	printf (" 1.read %x", rval);
	93	printf (" 2.read %x", (vu_long ) t);
	94	printf (" 3.read %x", (vu_long ) t);
	95	break;
	96	}
	97	}
	98	}
	99	#endif
6d0f6bcf	100	#endif /* CONFIG_SYS_RAMBOOT */
c1896004 WD	101
	102	dramsize = ((1 << ((vu_long )MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
	103
	104	/* return total ram size */
	105	return dramsize;
	106	}
	107
	108	/*****************************************************************************
	109	* print board identification
	110	*****************************************************************************/
	111	int checkboard (void)
	112	{
	113	#if defined (CONFIG_EVAL5200)
	114	puts ("Board: EMK TOP5200 on EVAL5200\n");
	115	#else
4d13cbad WD	116	#if defined (CONFIG_LITE5200)
	117	puts ("Board: LITE5200\n");
	118	#else
c1896004 WD	119	#if defined (CONFIG_MINI5200)
	120	puts ("Board: EMK TOP5200 on MINI5200\n");
	121	#else
	122	puts ("Board: EMK TOP5200\n");
	123	#endif
4d13cbad	124	#endif
c1896004 WD	125	#endif
	126	return 0;
	127	}
	128
	129	/*****************************************************************************
	130	* prepare for FLASH detection
	131	*****************************************************************************/
	132	void flash_preinit(void)
	133	{
	134	/*
	135	* Now, when we are in RAM, enable flash write
	136	* access for detection process.
	137	* Note that CS_BOOT cannot be cleared when
	138	* executing in flash.
	139	*/
	140	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	141	}
	142
	143	/*****************************************************************************
	144	* finalize FLASH setup
	145	*****************************************************************************/
	146	void flash_afterinit(uint bank, ulong start, ulong size)
	147	{
	148	if (bank == 0) { /* adjust mapping */
	149	(vu_long )MPC5XXX_BOOTCS_START =
	150	(vu_long )MPC5XXX_CS0_START = START_REG(start);
	151	(vu_long )MPC5XXX_BOOTCS_STOP =
	152	(vu_long )MPC5XXX_CS0_STOP = STOP_REG(start, size);
	153	}
	154	}
	155
	156	/*****************************************************************************
	157	* otherinits after RAM is there and we are relocated to RAM
	158	* note: though this is an int function, nobody cares for the result!
	159	*****************************************************************************/
	160	int misc_init_r (void)
	161	{
4d13cbad	162	#if !defined (CONFIG_LITE5200)
c1896004	163	/* read 'factory' part of EEPROM */
63e73c9a WD	164	extern void read_factory_r (void);
63e73c9a WD	165	read_factory_r ();
4d13cbad	166	#endif
c1896004 WD	167	return (0);
	168	}
	169
	170	/*****************************************************************************
	171	* initialize the PCI system
	172	*****************************************************************************/
	173	#ifdef CONFIG_PCI
	174	static struct pci_controller hose;
	175
	176	extern void pci_mpc5xxx_init(struct pci_controller *);
	177
	178	void pci_init_board(void)
	179	{
	180	pci_mpc5xxx_init(&hose);
	181	}
	182	#endif
4d13cbad WD	183
4d13cbad WD	184	/*****************************************************************************
498b8db7	185	* provide the IDE Reset Function
4d13cbad	186	*****************************************************************************/
77a31854	187	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
498b8db7	188
498b8db7 WD	189	void init_ide_reset (void)
	190	{
	191	debug ("init_ide_reset\n");
	192
dd520bf3	193	/* Configure PSC1_4 as GPIO output for ATA reset */
498b8db7 WD	194	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	195	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	196	}
	197
4d13cbad WD	198	void ide_set_reset (int idereset)
4d13cbad WD	199	{
498b8db7 WD	200	debug ("ide_reset(%d)\n", idereset);
498b8db7 WD	201
4d13cbad	202	if (idereset) {
dae80f3c	203	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
4d13cbad	204	} else {
dae80f3c	205	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
4d13cbad	206	}
4d13cbad	207	}
77a31854	208	#endif