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16f21704 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <i2c.h> | |
26 | #include "eric.h" | |
27 | #include <asm/processor.h> | |
28 | ||
0c8721a4 WD |
29 | #define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */ |
30 | #define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */ | |
31 | #define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ | |
32 | #define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ | |
16f21704 | 33 | |
bbeff30c SR |
34 | void sdram_init(void); |
35 | ||
c837dcb1 | 36 | int board_early_init_f (void) |
16f21704 WD |
37 | { |
38 | ||
39 | /*-------------------------------------------------------------------------+ | |
40 | | Interrupt controller setup for the ERIC board. | |
41 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
42 | | IRQ 16 405GP internally generated; active low; level sensitive | |
43 | | IRQ 17-24 RESERVED | |
44 | | IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive | |
45 | | IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive | |
46 | | IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive | |
47 | | indicates NO Power or HOST RESET active | |
48 | | check GPIO7 (HOST RESET#) and GPIO8 (NO Power#) | |
49 | | for real IRQ source | |
50 | | IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive | |
51 | | IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive | |
52 | | IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive | |
53 | | IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive | |
54 | | -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting | |
0c8721a4 | 55 | | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR, |
16f21704 WD |
56 | | else tristate) |
57 | | Note for ERIC board: | |
58 | | An interrupt taken for the HOST (IRQ 28) indicates that | |
59 | | the HOST wrote a "1" to one of the following locations | |
60 | | - VGA CRT_GPIO0 (if R1216 is loaded) | |
61 | | - VGA CRT_GPIO1 (if R1217 is loaded) | |
62 | | | |
63 | +-------------------------------------------------------------------------*/ | |
64 | ||
65 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
66 | mtdcr (uicer, 0x00000000); /* disable all ints */ | |
67 | mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */ | |
68 | mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ | |
69 | mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */ | |
70 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
71 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
72 | ||
73 | mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ | |
74 | ||
0c8721a4 WD |
75 | out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */ |
76 | out32 (PPC405GP_GPIO0_TCR, 0x7E400000); | |
16f21704 WD |
77 | |
78 | return 0; | |
79 | } | |
80 | ||
81 | ||
82 | /* ------------------------------------------------------------------------- */ | |
83 | ||
84 | /* | |
85 | * Check Board Identity: | |
86 | */ | |
87 | ||
88 | int checkboard (void) | |
89 | { | |
77ddac94 WD |
90 | char *s = getenv ("serial#"); |
91 | char *e; | |
16f21704 WD |
92 | |
93 | puts ("Board: "); | |
94 | ||
95 | if (!s || strncmp (s, "ERIC", 9)) { | |
96 | puts ("### No HW ID - assuming ERIC"); | |
97 | } else { | |
98 | for (e = s; *e; ++e) { | |
99 | if (*e == ' ') | |
100 | break; | |
101 | } | |
102 | ||
103 | for (; s < e; ++s) { | |
104 | putc (*s); | |
105 | } | |
106 | } | |
107 | ||
108 | ||
109 | putc ('\n'); | |
110 | ||
111 | return (0); | |
112 | } | |
113 | ||
114 | ||
115 | /* ------------------------------------------------------------------------- */ | |
116 | /* ------------------------------------------------------------------------- */ | |
117 | /* ------------------------------------------------------------------------- */ | |
118 | /* | |
119 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
120 | the necessary info for SDRAM controller configuration | |
121 | */ | |
122 | /* ------------------------------------------------------------------------- */ | |
123 | /* ------------------------------------------------------------------------- */ | |
9973e3c6 | 124 | phys_size_t initdram (int board_type) |
16f21704 WD |
125 | { |
126 | #ifndef CONFIG_ERIC | |
127 | int i; | |
128 | unsigned char datain[128]; | |
129 | int TotalSize; | |
130 | #endif | |
131 | ||
bbeff30c SR |
132 | /* |
133 | * ToDo: Move the asm init routine sdram_init() to this C file, | |
134 | * or even better use some common ppc4xx code available | |
135 | * in cpu/ppc4xx | |
136 | */ | |
137 | sdram_init(); | |
16f21704 WD |
138 | |
139 | #ifdef CONFIG_ERIC | |
140 | /* | |
141 | * we have no EEPROM on ERIC | |
142 | * so let init.S do the init job for SDRAM | |
143 | * and simply return 32MByte here | |
144 | */ | |
6d0f6bcf | 145 | return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024); |
16f21704 WD |
146 | #else |
147 | ||
148 | /* Read Serial Presence Detect Information */ | |
149 | for (i = 0; i < 128; i++) | |
150 | datain[i] = 127; | |
151 | i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128); | |
152 | printf ("\nReading DIMM...\n"); | |
153 | #if 0 | |
154 | for (i = 0; i < 128; i++) { | |
155 | printf ("%d=0x%x ", i, datain[i]); | |
156 | if (((i + 1) % 10) == 0) | |
157 | printf ("\n"); | |
158 | } | |
159 | printf ("\n"); | |
160 | #endif | |
161 | ||
162 | /*****************************/ | |
163 | /* Retrieve interesting data */ | |
164 | /*****************************/ | |
165 | /* size of a SDRAM bank */ | |
166 | /* Number of bytes per side / number of banks per side */ | |
167 | if (datain[31] == 0x08) | |
168 | TotalSize = 32; | |
169 | else if (datain[31] == 0x10) | |
170 | TotalSize = 64; | |
171 | else { | |
172 | printf ("IIC READ ERROR!!!\n"); | |
173 | TotalSize = 32; | |
174 | } | |
175 | ||
176 | /* single-sided DIMM or double-sided DIMM? */ | |
177 | if (datain[5] != 1) { | |
178 | /* double-sided DIMM => SDRAM banks 0..3 are valid */ | |
179 | printf ("double-sided DIMM\n"); | |
180 | TotalSize *= 2; | |
181 | } | |
182 | /* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */ | |
183 | else { | |
184 | printf ("single-sided DIMM\n"); | |
185 | } | |
186 | ||
187 | ||
188 | /* return size in Mb unit => *(1024*1024) */ | |
189 | return (TotalSize * 1024 * 1024); | |
190 | #endif | |
191 | } | |
192 | ||
193 | /* ------------------------------------------------------------------------- */ | |
194 | ||
195 | int testdram (void) | |
196 | { | |
197 | /* TODO: XXX XXX XXX */ | |
198 | printf ("test: xxx MB - ok\n"); | |
199 | ||
200 | return (0); | |
201 | } | |
202 | ||
203 | /* ------------------------------------------------------------------------- */ |