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e09f7ab5 MF |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
b706d635 | 26 | #if defined(CONFIG_CMD_NAND) |
e09f7ab5 MF |
27 | #include <asm/io.h> |
28 | #include <nand.h> | |
29 | ||
30 | /* | |
31 | * hardware specific access to control-lines | |
32 | */ | |
33 | static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) | |
34 | { | |
35 | switch(cmd) { | |
36 | case NAND_CTL_SETCLE: | |
37 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); | |
38 | break; | |
39 | case NAND_CTL_CLRCLE: | |
40 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); | |
41 | break; | |
42 | case NAND_CTL_SETALE: | |
43 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); | |
44 | break; | |
45 | case NAND_CTL_CLRALE: | |
46 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); | |
47 | break; | |
48 | case NAND_CTL_SETNCE: | |
49 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); | |
50 | break; | |
51 | case NAND_CTL_CLRNCE: | |
52 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); | |
53 | break; | |
54 | } | |
55 | } | |
56 | ||
57 | ||
58 | /* | |
59 | * read device ready pin | |
60 | */ | |
61 | static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) | |
62 | { | |
63 | if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) | |
64 | return 1; | |
65 | return 0; | |
66 | } | |
67 | ||
68 | ||
69 | int board_nand_init(struct nand_chip *nand) | |
70 | { | |
71 | /* | |
72 | * Set NAND-FLASH GPIO signals to defaults | |
73 | */ | |
74 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); | |
75 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); | |
76 | ||
77 | /* | |
78 | * Initialize nand_chip structure | |
79 | */ | |
80 | nand->hwcontrol = esd405ep_nand_hwcontrol; | |
81 | nand->dev_ready = esd405ep_nand_device_ready; | |
82 | nand->eccmode = NAND_ECC_SOFT; | |
83 | nand->chip_delay = NAND_BIG_DELAY_US; | |
84 | nand->options = NAND_SAMSUNG_LP_OPTIONS; | |
85 | return 0; | |
86 | } | |
b706d635 | 87 | #endif |