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Commit | Line | Data |
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c609719b | 1 | /* |
6f4474e8 | 2 | * (C) Copyright 2001-2003 |
c609719b WD |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
6f35c531 | 26 | #include <asm/io.h> |
c609719b | 27 | #include <command.h> |
c609719b | 28 | #include <malloc.h> |
87663b1c | 29 | #include <net.h> |
6f35c531 | 30 | #include <pci.h> |
c609719b | 31 | |
d87080b7 WD |
32 | DECLARE_GLOBAL_DATA_PTR; |
33 | ||
4ef218f6 | 34 | extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ |
c609719b WD |
35 | #if 0 |
36 | #define FPGA_DEBUG | |
37 | #endif | |
38 | ||
39 | /* fpga configuration data - generated by bin2cc */ | |
40 | const unsigned char fpgadata[] = | |
41 | { | |
42 | #ifdef CONFIG_CPCI405_VER2 | |
d4629c8c SR |
43 | # ifdef CONFIG_CPCI405AB |
44 | # include "fpgadata_cpci405ab.c" | |
45 | # else | |
46 | # include "fpgadata_cpci4052.c" | |
47 | # endif | |
c609719b WD |
48 | #else |
49 | # include "fpgadata_cpci405.c" | |
50 | #endif | |
51 | }; | |
52 | ||
53 | /* | |
54 | * include common fpga code (for esd boards) | |
55 | */ | |
56 | #include "../common/fpga.c" | |
87663b1c SR |
57 | #include "../common/auto_update.h" |
58 | ||
59 | #ifdef CONFIG_CPCI405AB | |
60 | au_image_t au_image[] = { | |
61 | {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, | |
62 | {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, | |
63 | {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, | |
64 | {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, | |
65 | {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, | |
66 | }; | |
67 | #else | |
68 | #ifdef CONFIG_CPCI405_VER2 | |
69 | au_image_t au_image[] = { | |
70 | {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, | |
71 | {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, | |
72 | {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, | |
73 | {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, | |
74 | {"cpci4052/postinst.img", 0, 0, AU_SCRIPT}, | |
75 | }; | |
76 | #else | |
77 | au_image_t au_image[] = { | |
78 | {"cpci405/preinst.img", 0, -1, AU_SCRIPT}, | |
79 | {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR}, | |
80 | {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR}, | |
81 | {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE}, | |
82 | {"cpci405/postinst.img", 0, 0, AU_SCRIPT}, | |
83 | }; | |
84 | #endif | |
85 | #endif | |
86 | ||
87 | int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); | |
88 | ||
c609719b | 89 | /* Prototypes */ |
6f4474e8 | 90 | int cpci405_version(void); |
eedcd078 | 91 | int gunzip(void *, int, unsigned char *, unsigned long *); |
87663b1c | 92 | void lxt971_no_sleep(void); |
c609719b | 93 | |
c837dcb1 | 94 | int board_early_init_f (void) |
c609719b WD |
95 | { |
96 | #ifndef CONFIG_CPCI405_VER2 | |
97 | int index, len, i; | |
98 | int status; | |
99 | #endif | |
100 | ||
101 | #ifdef FPGA_DEBUG | |
c609719b WD |
102 | /* set up serial port with default baudrate */ |
103 | (void) get_clocks (); | |
104 | gd->baudrate = CONFIG_BAUDRATE; | |
105 | serial_init (); | |
106 | console_init_f(); | |
107 | #endif | |
108 | ||
109 | /* | |
110 | * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) | |
111 | */ | |
4ef218f6 | 112 | out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ |
6d0f6bcf JCPV |
113 | out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ |
114 | out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ | |
4ef218f6 | 115 | out32(GPIO0_OR, 0); /* pull prg low */ |
c609719b WD |
116 | |
117 | /* | |
118 | * Boot onboard FPGA | |
119 | */ | |
120 | #ifndef CONFIG_CPCI405_VER2 | |
6f4474e8 | 121 | if (cpci405_version() == 1) { |
c609719b WD |
122 | status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); |
123 | if (status != 0) { | |
124 | /* booting FPGA failed */ | |
125 | #ifndef FPGA_DEBUG | |
c609719b WD |
126 | /* set up serial port with default baudrate */ |
127 | (void) get_clocks (); | |
128 | gd->baudrate = CONFIG_BAUDRATE; | |
129 | serial_init (); | |
130 | console_init_f(); | |
131 | #endif | |
132 | printf("\nFPGA: Booting failed "); | |
133 | switch (status) { | |
134 | case ERROR_FPGA_PRG_INIT_LOW: | |
135 | printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); | |
136 | break; | |
137 | case ERROR_FPGA_PRG_INIT_HIGH: | |
138 | printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); | |
139 | break; | |
140 | case ERROR_FPGA_PRG_DONE: | |
141 | printf("(Timeout: DONE not high after programming FPGA)\n "); | |
142 | break; | |
143 | } | |
144 | ||
145 | /* display infos on fpgaimage */ | |
146 | index = 15; | |
147 | for (i=0; i<4; i++) { | |
148 | len = fpgadata[index]; | |
149 | printf("FPGA: %s\n", &(fpgadata[index+1])); | |
150 | index += len+3; | |
151 | } | |
152 | putc ('\n'); | |
153 | /* delayed reboot */ | |
154 | for (i=20; i>0; i--) { | |
155 | printf("Rebooting in %2d seconds \r",i); | |
156 | for (index=0;index<1000;index++) | |
157 | udelay(1000); | |
158 | } | |
159 | putc ('\n'); | |
160 | do_reset(NULL, 0, 0, NULL); | |
161 | } | |
162 | } | |
163 | #endif /* !CONFIG_CPCI405_VER2 */ | |
164 | ||
165 | /* | |
166 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
167 | * IRQ 16 405GP internally generated; active low; level sensitive | |
168 | * IRQ 17-24 RESERVED | |
169 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
170 | * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive | |
171 | * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive | |
172 | * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive | |
173 | * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
174 | * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive | |
175 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
176 | */ | |
4ef218f6 WD |
177 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
178 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
179 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
6f35c531 | 180 | #ifdef CONFIG_CPCI405_6U |
6f4474e8 | 181 | if (cpci405_version() == 3) { |
4ef218f6 | 182 | mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ |
6f4474e8 | 183 | } else { |
4ef218f6 | 184 | mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ |
6f4474e8 | 185 | } |
6f35c531 | 186 | #else |
4ef218f6 | 187 | mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ |
6f35c531 | 188 | #endif |
4ef218f6 WD |
189 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
190 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
191 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
c609719b WD |
192 | |
193 | return 0; | |
194 | } | |
195 | ||
c609719b WD |
196 | /* ------------------------------------------------------------------------- */ |
197 | ||
198 | int ctermm2(void) | |
199 | { | |
200 | #ifdef CONFIG_CPCI405_VER2 | |
4ef218f6 | 201 | return 0; /* no, board is cpci405 */ |
c609719b WD |
202 | #else |
203 | if ((*(unsigned char *)0xf0000400 == 0x00) && | |
204 | (*(unsigned char *)0xf0000401 == 0x01)) | |
4ef218f6 | 205 | return 0; /* no, board is cpci405 */ |
c609719b | 206 | else |
4ef218f6 | 207 | return -1; /* yes, board is cterm-m2 */ |
c609719b WD |
208 | #endif |
209 | } | |
210 | ||
c609719b WD |
211 | int cpci405_host(void) |
212 | { | |
213 | if (mfdcr(strap) & PSR_PCI_ARBIT_EN) | |
4ef218f6 | 214 | return -1; /* yes, board is cpci405 host */ |
c609719b | 215 | else |
4ef218f6 | 216 | return 0; /* no, board is cpci405 adapter */ |
c609719b WD |
217 | } |
218 | ||
6f4474e8 | 219 | int cpci405_version(void) |
c609719b WD |
220 | { |
221 | unsigned long cntrl0Reg; | |
222 | unsigned long value; | |
223 | ||
224 | /* | |
6f4474e8 | 225 | * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) |
c609719b WD |
226 | */ |
227 | cntrl0Reg = mfdcr(cntrl0); | |
6f4474e8 | 228 | mtdcr(cntrl0, cntrl0Reg | 0x03000000); |
6f35c531 MF |
229 | out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); |
230 | out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); | |
4ef218f6 WD |
231 | udelay(1000); /* wait some time before reading input */ |
232 | value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ | |
c609719b WD |
233 | |
234 | /* | |
6f4474e8 | 235 | * Restore GPIO settings |
c609719b WD |
236 | */ |
237 | mtdcr(cntrl0, cntrl0Reg); | |
238 | ||
6f4474e8 SR |
239 | switch (value) { |
240 | case 0x00180000: | |
241 | /* CS2==1 && CS3==1 -> version 1 */ | |
242 | return 1; | |
243 | case 0x00080000: | |
244 | /* CS2==0 && CS3==1 -> version 2 */ | |
245 | return 2; | |
246 | case 0x00100000: | |
6f35c531 | 247 | /* CS2==1 && CS3==0 -> version 3 or 6U board */ |
6f4474e8 SR |
248 | return 3; |
249 | case 0x00000000: | |
250 | /* CS2==0 && CS3==0 -> version 4 */ | |
251 | return 4; | |
252 | default: | |
253 | /* should not be reached! */ | |
254 | return 2; | |
255 | } | |
c609719b WD |
256 | } |
257 | ||
c609719b WD |
258 | int misc_init_r (void) |
259 | { | |
afcc4a74 | 260 | unsigned long cntrl0Reg; |
c609719b | 261 | |
87663b1c SR |
262 | /* adjust flash start and offset */ |
263 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
264 | gd->bd->bi_flashoffset = 0; | |
265 | ||
c609719b | 266 | #ifdef CONFIG_CPCI405_VER2 |
87663b1c | 267 | { |
c609719b WD |
268 | unsigned char *dst; |
269 | ulong len = sizeof(fpgadata); | |
270 | int status; | |
271 | int index; | |
272 | int i; | |
c609719b WD |
273 | |
274 | /* | |
275 | * On CPCI-405 version 2 the environment is saved in eeprom! | |
276 | * FPGA can be gzip compressed (malloc) and booted this late. | |
277 | */ | |
6f4474e8 | 278 | if (cpci405_version() >= 2) { |
c609719b WD |
279 | /* |
280 | * Setup GPIO pins (CS6+CS7 as GPIO) | |
281 | */ | |
282 | cntrl0Reg = mfdcr(cntrl0); | |
283 | mtdcr(cntrl0, cntrl0Reg | 0x00300000); | |
284 | ||
6d0f6bcf JCPV |
285 | dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
286 | if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { | |
c609719b WD |
287 | printf ("GUNZIP ERROR - must RESET board to recover\n"); |
288 | do_reset (NULL, 0, 0, NULL); | |
289 | } | |
290 | ||
291 | status = fpga_boot(dst, len); | |
292 | if (status != 0) { | |
293 | printf("\nFPGA: Booting failed "); | |
294 | switch (status) { | |
295 | case ERROR_FPGA_PRG_INIT_LOW: | |
296 | printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); | |
297 | break; | |
298 | case ERROR_FPGA_PRG_INIT_HIGH: | |
299 | printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); | |
300 | break; | |
301 | case ERROR_FPGA_PRG_DONE: | |
302 | printf("(Timeout: DONE not high after programming FPGA)\n "); | |
303 | break; | |
304 | } | |
305 | ||
306 | /* display infos on fpgaimage */ | |
307 | index = 15; | |
308 | for (i=0; i<4; i++) { | |
309 | len = dst[index]; | |
310 | printf("FPGA: %s\n", &(dst[index+1])); | |
311 | index += len+3; | |
312 | } | |
313 | putc ('\n'); | |
314 | /* delayed reboot */ | |
315 | for (i=20; i>0; i--) { | |
316 | printf("Rebooting in %2d seconds \r",i); | |
317 | for (index=0;index<1000;index++) | |
318 | udelay(1000); | |
319 | } | |
320 | putc ('\n'); | |
321 | do_reset(NULL, 0, 0, NULL); | |
322 | } | |
323 | ||
324 | /* restore gpio/cs settings */ | |
325 | mtdcr(cntrl0, cntrl0Reg); | |
326 | ||
327 | puts("FPGA: "); | |
328 | ||
329 | /* display infos on fpgaimage */ | |
330 | index = 15; | |
331 | for (i=0; i<4; i++) { | |
332 | len = dst[index]; | |
333 | printf("%s ", &(dst[index+1])); | |
334 | index += len+3; | |
335 | } | |
336 | putc ('\n'); | |
337 | ||
338 | free(dst); | |
6f4474e8 SR |
339 | |
340 | /* | |
341 | * Reset FPGA via FPGA_DATA pin | |
342 | */ | |
343 | SET_FPGA(FPGA_PRG | FPGA_CLK); | |
344 | udelay(1000); /* wait 1ms */ | |
345 | SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); | |
346 | udelay(1000); /* wait 1ms */ | |
347 | ||
6f35c531 | 348 | #ifdef CONFIG_CPCI405_6U |
6f4474e8 | 349 | if (cpci405_version() == 3) { |
6d0f6bcf JCPV |
350 | volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; |
351 | volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR; | |
6f4474e8 SR |
352 | |
353 | /* | |
354 | * Enable outputs in fpga on version 3 board | |
355 | */ | |
6d0f6bcf | 356 | *fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT; |
6f4474e8 SR |
357 | |
358 | /* | |
359 | * Set outputs to 0 | |
360 | */ | |
361 | *leds = 0x00; | |
362 | ||
363 | /* | |
364 | * Reset external DUART | |
365 | */ | |
6d0f6bcf | 366 | *fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET; |
6f4474e8 | 367 | udelay(100); |
6d0f6bcf | 368 | *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET); |
6f4474e8 | 369 | } |
6f35c531 | 370 | #endif |
c609719b WD |
371 | } |
372 | else { | |
6f4474e8 SR |
373 | puts("\n*** U-Boot Version does not match Board Version!\n"); |
374 | puts("*** CPCI-405 Version 1.x detected!\n"); | |
375 | puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); | |
c609719b | 376 | } |
87663b1c | 377 | } |
c609719b WD |
378 | |
379 | #else /* CONFIG_CPCI405_VER2 */ | |
380 | ||
87663b1c | 381 | #if 0 /* test-only: code-plug now not relavant for ip-address any more */ |
c609719b WD |
382 | /* |
383 | * Generate last byte of ip-addr from code-plug @ 0xf0000400 | |
384 | */ | |
385 | if (ctermm2()) { | |
386 | char str[32]; | |
387 | unsigned char ipbyte = *(unsigned char *)0xf0000400; | |
388 | ||
389 | /* | |
390 | * Only overwrite ip-addr with allowed values | |
391 | */ | |
392 | if ((ipbyte != 0x00) && (ipbyte != 0xff)) { | |
393 | bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; | |
394 | sprintf(str, "%ld.%ld.%ld.%ld", | |
395 | (bd->bi_ip_addr & 0xff000000) >> 24, | |
396 | (bd->bi_ip_addr & 0x00ff0000) >> 16, | |
397 | (bd->bi_ip_addr & 0x0000ff00) >> 8, | |
398 | (bd->bi_ip_addr & 0x000000ff)); | |
399 | setenv("ipaddr", str); | |
400 | } | |
401 | } | |
87663b1c | 402 | #endif |
c609719b | 403 | |
6f4474e8 SR |
404 | if (cpci405_version() >= 2) { |
405 | puts("\n*** U-Boot Version does not match Board Version!\n"); | |
406 | puts("*** CPCI-405 Board Version 2.x detected!\n"); | |
407 | puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n"); | |
c609719b WD |
408 | } |
409 | ||
410 | #endif /* CONFIG_CPCI405_VER2 */ | |
411 | ||
afcc4a74 SR |
412 | /* |
413 | * Select cts (and not dsr) on uart1 | |
414 | */ | |
415 | cntrl0Reg = mfdcr(cntrl0); | |
416 | mtdcr(cntrl0, cntrl0Reg | 0x00001000); | |
417 | ||
c609719b WD |
418 | return (0); |
419 | } | |
420 | ||
c609719b WD |
421 | /* |
422 | * Check Board Identity: | |
423 | */ | |
424 | ||
425 | int checkboard (void) | |
426 | { | |
427 | #ifndef CONFIG_CPCI405_VER2 | |
428 | int index; | |
429 | int len; | |
430 | #endif | |
77ddac94 | 431 | char str[64]; |
c609719b | 432 | int i = getenv_r ("serial#", str, sizeof(str)); |
6f4474e8 | 433 | unsigned short ver; |
c609719b WD |
434 | |
435 | puts ("Board: "); | |
436 | ||
437 | if (i == -1) { | |
438 | puts ("### No HW ID - assuming CPCI405"); | |
439 | } else { | |
440 | puts(str); | |
441 | } | |
442 | ||
6f4474e8 SR |
443 | ver = cpci405_version(); |
444 | printf(" (Ver %d.x, ", ver); | |
c609719b | 445 | |
6f4474e8 SR |
446 | #if 0 /* test-only */ |
447 | if (ver >= 2) { | |
6d0f6bcf | 448 | volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1; |
6f4474e8 | 449 | |
6d0f6bcf | 450 | if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) { |
6f4474e8 SR |
451 | puts ("FLASH Bank B, "); |
452 | } else { | |
453 | puts ("FLASH Bank A, "); | |
454 | } | |
455 | } | |
c609719b WD |
456 | #endif |
457 | ||
458 | if (ctermm2()) { | |
77ddac94 | 459 | char str[4]; |
1b554406 SR |
460 | |
461 | /* | |
462 | * Read board-id and save in env-variable | |
463 | */ | |
464 | sprintf(str, "%d", *(unsigned char *)0xf0000400); | |
465 | setenv("boardid", str); | |
466 | printf("CTERM-M2 - Id=%s)", str); | |
c609719b WD |
467 | } else { |
468 | if (cpci405_host()) { | |
469 | puts ("PCI Host Version)"); | |
470 | } else { | |
471 | puts ("PCI Adapter Version)"); | |
472 | } | |
473 | } | |
474 | ||
475 | #ifndef CONFIG_CPCI405_VER2 | |
4ef218f6 | 476 | puts ("\nFPGA: "); |
c609719b WD |
477 | |
478 | /* display infos on fpgaimage */ | |
479 | index = 15; | |
480 | for (i=0; i<4; i++) { | |
481 | len = fpgadata[index]; | |
482 | printf("%s ", &(fpgadata[index+1])); | |
483 | index += len+3; | |
484 | } | |
485 | #endif | |
486 | ||
487 | putc ('\n'); | |
c609719b WD |
488 | return 0; |
489 | } | |
490 | ||
6f35c531 | 491 | void reset_phy(void) |
c609719b | 492 | { |
6f35c531 | 493 | #ifdef CONFIG_LXT971_NO_SLEEP |
c609719b | 494 | |
6f35c531 MF |
495 | /* |
496 | * Disable sleep mode in LXT971 | |
497 | */ | |
498 | lxt971_no_sleep(); | |
499 | #endif | |
c609719b WD |
500 | } |
501 | ||
c609719b WD |
502 | #ifdef CONFIG_CPCI405_VER2 |
503 | #ifdef CONFIG_IDE_RESET | |
504 | ||
505 | void ide_set_reset(int on) | |
506 | { | |
6d0f6bcf | 507 | volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; |
c609719b WD |
508 | |
509 | /* | |
510 | * Assert or deassert CompactFlash Reset Pin | |
511 | */ | |
512 | if (on) { /* assert RESET */ | |
6d0f6bcf | 513 | *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET); |
c609719b | 514 | } else { /* release RESET */ |
6d0f6bcf | 515 | *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET; |
c609719b WD |
516 | } |
517 | } | |
518 | ||
519 | #endif /* CONFIG_IDE_RESET */ | |
520 | #endif /* CONFIG_CPCI405_VER2 */ | |
521 | ||
466fff1a | 522 | #if defined(CONFIG_PCI) |
6f35c531 MF |
523 | void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
524 | { | |
525 | unsigned char int_line = 0xff; | |
526 | ||
527 | /* | |
528 | * Write pci interrupt line register (cpci405 specific) | |
529 | */ | |
530 | switch (PCI_DEV(dev) & 0x03) { | |
531 | case 0: | |
532 | int_line = 27 + 2; | |
533 | break; | |
534 | case 1: | |
535 | int_line = 27 + 3; | |
536 | break; | |
537 | case 2: | |
538 | int_line = 27 + 0; | |
539 | break; | |
540 | case 3: | |
541 | int_line = 27 + 1; | |
542 | break; | |
543 | } | |
544 | ||
545 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); | |
546 | } | |
547 | ||
548 | int pci_pre_init(struct pci_controller *hose) | |
549 | { | |
550 | hose->fixup_irq = cpci405_pci_fixup_irq; | |
551 | return 1; | |
552 | } | |
466fff1a | 553 | #endif /* defined(CONFIG_PCI) */ |
6f35c531 MF |
554 | |
555 | ||
1b554406 SR |
556 | #ifdef CONFIG_CPCI405AB |
557 | ||
6d0f6bcf JCPV |
558 | #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ |
559 | |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR) | |
560 | #define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ | |
561 | &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) | |
562 | #define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \ | |
563 | & CONFIG_SYS_FPGA_MODE_1WIRE) | |
1b554406 SR |
564 | |
565 | /* | |
566 | * Generate a 1-wire reset, return 1 if no presence detect was found, | |
567 | * return 0 otherwise. | |
568 | * (NOTE: Does not handle alarm presence from DS2404/DS1994) | |
569 | */ | |
570 | int OWTouchReset(void) | |
d4629c8c | 571 | { |
1b554406 SR |
572 | int result; |
573 | ||
574 | ONE_WIRE_CLEAR; | |
575 | udelay(480); | |
576 | ONE_WIRE_SET; | |
577 | udelay(70); | |
578 | ||
579 | result = ONE_WIRE_GET; | |
580 | ||
581 | udelay(410); | |
582 | return result; | |
583 | } | |
584 | ||
1b554406 SR |
585 | /* |
586 | * Send 1 a 1-wire write bit. | |
587 | * Provide 10us recovery time. | |
588 | */ | |
589 | void OWWriteBit(int bit) | |
590 | { | |
591 | if (bit) { | |
592 | /* | |
593 | * write '1' bit | |
594 | */ | |
595 | ONE_WIRE_CLEAR; | |
596 | udelay(6); | |
597 | ONE_WIRE_SET; | |
598 | udelay(64); | |
599 | } else { | |
600 | /* | |
601 | * write '0' bit | |
602 | */ | |
603 | ONE_WIRE_CLEAR; | |
604 | udelay(60); | |
605 | ONE_WIRE_SET; | |
606 | udelay(10); | |
d4629c8c | 607 | } |
1b554406 SR |
608 | } |
609 | ||
1b554406 SR |
610 | /* |
611 | * Read a bit from the 1-wire bus and return it. | |
612 | * Provide 10us recovery time. | |
613 | */ | |
614 | int OWReadBit(void) | |
615 | { | |
616 | int result; | |
617 | ||
618 | ONE_WIRE_CLEAR; | |
619 | udelay(6); | |
620 | ONE_WIRE_SET; | |
621 | udelay(9); | |
622 | ||
623 | result = ONE_WIRE_GET; | |
624 | ||
625 | udelay(55); | |
626 | return result; | |
d4629c8c SR |
627 | } |
628 | ||
1b554406 SR |
629 | void OWWriteByte(int data) |
630 | { | |
631 | int loop; | |
632 | ||
633 | for (loop=0; loop<8; loop++) { | |
634 | OWWriteBit(data & 0x01); | |
635 | data >>= 1; | |
636 | } | |
637 | } | |
638 | ||
1b554406 | 639 | int OWReadByte(void) |
d4629c8c | 640 | { |
1b554406 SR |
641 | int loop, result = 0; |
642 | ||
643 | for (loop=0; loop<8; loop++) { | |
644 | result >>= 1; | |
645 | if (OWReadBit()) { | |
646 | result |= 0x80; | |
647 | } | |
d4629c8c | 648 | } |
1b554406 SR |
649 | |
650 | return result; | |
d4629c8c SR |
651 | } |
652 | ||
1b554406 SR |
653 | int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
654 | { | |
655 | volatile unsigned short val; | |
656 | int result; | |
657 | int i; | |
658 | unsigned char ow_id[6]; | |
77ddac94 | 659 | char str[32]; |
1b554406 SR |
660 | unsigned char ow_crc; |
661 | ||
662 | /* | |
663 | * Clear 1-wire bit (open drain with pull-up) | |
664 | */ | |
665 | val = *(volatile unsigned short *)0xf0400000; | |
666 | val &= ~0x1000; /* clear 1-wire bit */ | |
667 | *(volatile unsigned short *)0xf0400000 = val; | |
668 | ||
669 | result = OWTouchReset(); | |
670 | if (result != 0) { | |
671 | puts("No 1-wire device detected!\n"); | |
672 | } | |
673 | ||
674 | OWWriteByte(0x33); /* send read rom command */ | |
675 | OWReadByte(); /* skip family code ( == 0x01) */ | |
676 | for (i=0; i<6; i++) { | |
677 | ow_id[i] = OWReadByte(); | |
678 | } | |
679 | ow_crc = OWReadByte(); /* read crc */ | |
680 | ||
681 | sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]); | |
682 | printf("Setting environment variable 'ow_id' to %s\n", str); | |
683 | setenv("ow_id", str); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | U_BOOT_CMD( | |
688 | onewire, 1, 1, do_onewire, | |
689 | "onewire - Read 1-write ID\n", | |
690 | NULL | |
691 | ); | |
692 | ||
6d0f6bcf | 693 | #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ |
0e8d1586 | 694 | #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ |
87663b1c SR |
695 | |
696 | /* | |
697 | * Write backplane ip-address... | |
698 | */ | |
699 | int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
700 | { | |
87663b1c SR |
701 | bd_t *bd = gd->bd; |
702 | char *buf; | |
703 | ulong crc; | |
704 | char str[32]; | |
705 | char *ptr; | |
706 | IPaddr_t ipaddr; | |
707 | ||
0e8d1586 | 708 | buf = malloc(CONFIG_ENV_SIZE_2); |
6d0f6bcf | 709 | if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { |
87663b1c SR |
710 | puts("\nError reading backplane EEPROM!\n"); |
711 | } else { | |
0e8d1586 | 712 | crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); |
87663b1c SR |
713 | if (crc != *(ulong *)buf) { |
714 | printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); | |
715 | return -1; | |
716 | } | |
717 | ||
718 | /* | |
719 | * Find bp_ip | |
720 | */ | |
721 | ptr = strstr(buf+4, "bp_ip="); | |
722 | if (ptr == NULL) { | |
723 | printf("ERROR: bp_ip not found!\n"); | |
724 | return -1; | |
725 | } | |
726 | ptr += 6; | |
727 | ipaddr = string_to_ip(ptr); | |
728 | ||
729 | /* | |
730 | * Update whole ip-addr | |
731 | */ | |
732 | bd->bi_ip_addr = ipaddr; | |
733 | sprintf(str, "%ld.%ld.%ld.%ld", | |
734 | (bd->bi_ip_addr & 0xff000000) >> 24, | |
735 | (bd->bi_ip_addr & 0x00ff0000) >> 16, | |
736 | (bd->bi_ip_addr & 0x0000ff00) >> 8, | |
737 | (bd->bi_ip_addr & 0x000000ff)); | |
738 | setenv("ipaddr", str); | |
739 | printf("Updated ip_addr from bp_eeprom to %s!\n", str); | |
740 | } | |
741 | ||
742 | free(buf); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | U_BOOT_CMD( | |
747 | getbpip, 1, 1, do_get_bpip, | |
748 | "getbpip - Update IP-Address with Backplane IP-Address\n", | |
749 | NULL | |
750 | ); | |
751 | ||
752 | /* | |
753 | * Set and print backplane ip... | |
754 | */ | |
755 | int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
756 | { | |
757 | char *buf; | |
77ddac94 | 758 | char str[32]; |
87663b1c SR |
759 | ulong crc; |
760 | ||
761 | if (argc < 2) { | |
762 | puts("ERROR!\n"); | |
763 | return -1; | |
764 | } | |
765 | ||
766 | printf("Setting bp_ip to %s\n", argv[1]); | |
0e8d1586 JCPV |
767 | buf = malloc(CONFIG_ENV_SIZE_2); |
768 | memset(buf, 0, CONFIG_ENV_SIZE_2); | |
87663b1c SR |
769 | sprintf(str, "bp_ip=%s", argv[1]); |
770 | strcpy(buf+4, str); | |
0e8d1586 | 771 | crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); |
87663b1c SR |
772 | *(ulong *)buf = crc; |
773 | ||
6d0f6bcf | 774 | if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { |
87663b1c SR |
775 | puts("\nError writing backplane EEPROM!\n"); |
776 | } | |
777 | ||
778 | free(buf); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | U_BOOT_CMD( | |
783 | setbpip, 2, 1, do_set_bpip, | |
784 | "setbpip - Write Backplane IP-Address\n", | |
785 | NULL | |
786 | ); | |
787 | ||
1b554406 | 788 | #endif /* CONFIG_CPCI405AB */ |