]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/esd/dasa_sim/cmd_dasa_sim.c
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / esd / dasa_sim / cmd_dasa_sim.c
CommitLineData
affae2bf
WD
1/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#include <common.h>
26#include <command.h>
27#include <pci.h>
28
29#define OK 0
30#define ERROR (-1)
31
32#define TRUE 1
33#define FALSE 0
34
35
36extern u_long pci9054_iobase;
37
38
39/***************************************************************************
40 *
41 * Routines for PLX PCI9054 eeprom access
42 *
43 */
44
8bde7f77 45static unsigned int PciEepromReadLongVPD (int offs)
affae2bf 46{
8bde7f77
WD
47 unsigned int value;
48 unsigned int ret;
49 int count;
50
6d0f6bcf 51 pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
8bde7f77
WD
52 (offs << 16) | 0x0003);
53 count = 0;
54
55 for (;;) {
56 udelay (10 * 1000);
6d0f6bcf 57 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
8bde7f77
WD
58 if ((ret & 0x80000000) != 0) {
59 break;
60 } else {
61 count++;
62 if (count > 10) {
63 printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
64 break;
65 }
66 }
67 }
68
6d0f6bcf 69 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
8bde7f77
WD
70
71 return value;
affae2bf
WD
72}
73
74
8bde7f77 75static int PciEepromWriteLongVPD (int offs, unsigned int value)
affae2bf 76{
8bde7f77
WD
77 unsigned int ret;
78 int count;
79
6d0f6bcf
JCPV
80 pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
81 pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
8bde7f77
WD
82 (offs << 16) | 0x80000003);
83 count = 0;
84
85 for (;;) {
86 udelay (10 * 1000);
6d0f6bcf 87 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
8bde7f77
WD
88 if ((ret & 0x80000000) == 0) {
89 break;
90 } else {
91 count++;
92 if (count > 10) {
93 printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
94 break;
95 }
96 }
97 }
98
99 return TRUE;
affae2bf
WD
100}
101
102
8bde7f77 103static void showPci9054 (void)
affae2bf 104{
8bde7f77
WD
105 int val;
106 int l, i;
107
108 /* read 9054-values */
109 for (l = 0; l < 6; l++) {
110 printf ("%02x: ", l * 0x10);
111 for (i = 0; i < 4; i++) {
6d0f6bcf 112 pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
8bde7f77 113 l * 16 + i * 4,
77ddac94 114 (unsigned int *)&val);
8bde7f77
WD
115 printf ("%08x ", val);
116 }
117 printf ("\n");
118 }
119 printf ("\n");
120
121 for (l = 0; l < 7; l++) {
122 printf ("%02x: ", l * 0x10);
123 for (i = 0; i < 4; i++)
124 printf ("%08x ",
125 PciEepromReadLongVPD ((i + l * 4) * 4));
126 printf ("\n");
127 }
128 printf ("\n");
affae2bf
WD
129}
130
131
8bde7f77 132static void updatePci9054 (void)
affae2bf 133{
8bde7f77 134 int val;
affae2bf 135
8bde7f77
WD
136 /*
137 * Set EEPROM write-protect register to 0
138 */
139 out32 (pci9054_iobase + 0x0c,
140 in32 (pci9054_iobase + 0x0c) & 0xffff00ff);
affae2bf 141
8bde7f77
WD
142 /* Long Serial EEPROM Load Registers... */
143 val = PciEepromWriteLongVPD (0x00, 0x905410b5);
144 val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
145 val = PciEepromWriteLongVPD (0x08, 0x28140100);
affae2bf 146
8bde7f77
WD
147 val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
148 val = PciEepromWriteLongVPD (0x10, 0x00000000);
affae2bf 149
8bde7f77
WD
150 /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
151 val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
152 val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
affae2bf 153
8bde7f77
WD
154 val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
155 val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
affae2bf 156
8bde7f77
WD
157 val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
158 val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
affae2bf 159
8bde7f77 160 val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
affae2bf 161
8bde7f77
WD
162 val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
163 val = PciEepromWriteLongVPD (0x34, 0x00000000);
164 val = PciEepromWriteLongVPD (0x38, 0x00000000);
affae2bf 165
8bde7f77
WD
166 val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
167 val = PciEepromWriteLongVPD (0x40, 0x00000000);
affae2bf 168
8bde7f77
WD
169 /* Extra Long Serial EEPROM Load Registers... */
170 val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
affae2bf 171
8bde7f77
WD
172 /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
173 /* Offset to LAS1: Group 1: 0x00040000 */
174 /* Group 2: 0x00080000 */
175 /* Group 3: 0x000c0000 */
176 val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
177 val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
178 val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
affae2bf 179
8bde7f77 180 val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
affae2bf 181
8bde7f77 182 printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
affae2bf
WD
183}
184
185
8bde7f77 186static void clearPci9054 (void)
affae2bf 187{
8bde7f77 188 int val;
affae2bf 189
8bde7f77
WD
190 /*
191 * Set EEPROM write-protect register to 0
192 */
193 out32 (pci9054_iobase + 0x0c,
194 in32 (pci9054_iobase + 0x0c) & 0xffff00ff);
affae2bf 195
8bde7f77
WD
196 /* Long Serial EEPROM Load Registers... */
197 val = PciEepromWriteLongVPD (0x00, 0xffffffff);
198 val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
affae2bf 199
8bde7f77 200 printf ("Finished clearing PLX PCI9054 EEPROM!\n");
affae2bf
WD
201}
202
203
204/* ------------------------------------------------------------------------- */
8bde7f77
WD
205int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
206 char *argv[])
affae2bf 207{
8bde7f77
WD
208 if (strcmp (argv[1], "info") == 0) {
209 showPci9054 ();
210 return 0;
211 }
212
213 if (strcmp (argv[1], "update") == 0) {
214 updatePci9054 ();
215 return 0;
216 }
217
218 if (strcmp (argv[1], "clear") == 0) {
219 clearPci9054 ();
220 return 0;
221 }
222
223 printf ("Usage:\n%s\n", cmdtp->usage);
224 return 1;
affae2bf
WD
225
226}
227
0d498393
WD
228U_BOOT_CMD(
229 pci9054, 3, 1, do_pci9054,
8bde7f77
WD
230 "pci9054 - PLX PCI9054 EEPROM access\n",
231 "pci9054 info - print EEPROM values\n"
232 "pci9054 update - updates EEPROM with default values\n"
233);
234
affae2bf 235/* ------------------------------------------------------------------------- */