[people/ms/u-boot.git] / board / esd / pf5200 / pf5200.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * pf5200.c - main board support/init for the esd pf5200.
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>

#include "mt46v16m16-75.h"

void init_power_switch(void);

static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register: extended mode */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 *            is something else than 0x00000000.
 */

long int initdram(int board_type)
{
	ulong dramsize = 0;
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

	/* set tap delay */
	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);

	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
		/* let SDRAM CS1 start right after CS0 */
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
	} else {
#if 0
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
		/* let SDRAM CS1 start right after CS0 */
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
#else
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
		/* let SDRAM CS1 start right after CS0 */
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
#endif
	}

#if 0
	/* find RAM size using SDRAM CS1 only */
	sdram_start(0);
	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
	sdram_start(1);
	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
	sdram_start(0);
#endif
	/* set SDRAM CS1 size according to the amount of RAM found */

	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */

	init_power_switch();
	return (dramsize);
}

int checkboard(void)
{
	puts("Board: esd ParaFinder (pf5200)\n");
	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
}

void flash_afterinit(ulong size)
{
	if (size == 0x02000000) {
		/* adjust mapping */
		*(vu_long *) MPC5XXX_BOOTCS_START =
		    *(vu_long *) MPC5XXX_CS0_START =
		    START_REG(CFG_BOOTCS_START | size);
		*(vu_long *) MPC5XXX_BOOTCS_STOP =
		    *(vu_long *) MPC5XXX_CS0_STOP =
		    STOP_REG(CFG_BOOTCS_START | size, size);
	}
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void) {
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset(void)
{
	debug("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}

void ide_set_reset(int idereset)
{
	debug("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
	}
}
#endif

#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)

#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)

#define GPIO_WU6	0x40000000UL
#define GPIO_USB0       0x00010000UL
#define GPIO_USB9       0x08000000UL
#define GPIO_USB9S      0x00080000UL

void init_power_switch(void)
{
	debug("init_power_switch\n");

	/* Configure GPIO_WU6 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
	__asm__ volatile ("sync");

	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
	__asm__ volatile ("sync");

	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
	__asm__ volatile ("sync");

	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
		__asm__ volatile ("sync");
	}
	*(vu_char *) CFG_CS1_START = 0x02;	/* Red Power LED on */
	__asm__ volatile ("sync");

	*(vu_char *) (CFG_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
	__asm__ volatile ("sync");
}

void power_set_reset(int power)
{
	debug("ide_set_reset(%d)\n", power);

	if (power) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
		    0) {
			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
			    GPIO_USB0;
		}

	}
}

int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	power_set_reset(1);
	return (0);
}

U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL);

int phypower(int flag)
{
	u32 addr;
	vu_long *reg;
	int status;
	pci_dev_t dev;

	dev = PCI_BDF(0, 0x18, 0);
	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
	if (status == 0) {
		reg = (vu_long *) (addr + 0x00000040);
		*reg |= 0x40000000;
		__asm__ volatile ("sync");

		reg = (vu_long *) (addr + 0x001000c);
		*reg |= 0x20000000;
		__asm__ volatile ("sync");

		reg = (vu_long *) (addr + 0x0010004);
		if (flag != 0) {
			*reg &= ~0x20000000;
		} else {
			*reg |= 0x20000000;
		}
		__asm__ volatile ("sync");
	}
	return (status);
}

int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	int status;

	if (argv[1][0] == '0') {
		status = phypower(0);
	} else {
		status = phypower(1);
	}
	return (0);
}

U_BOOT_CMD(phypower, 2, 2, do_phypower,
	   "phypower- Switch power of ethernet phy\n", NULL);

int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	unsigned int addr;
	unsigned int size;
	int i;
	volatile unsigned long *ptr;

	addr = simple_strtol(argv[1], NULL, 16);
	size = simple_strtol(argv[2], NULL, 16);

	printf("\nWriting at addr %08x, size %08x.\n", addr, size);

	while (1) {
		ptr = (volatile unsigned long *)addr;
		for (i = 0; i < (size >> 2); i++) {
			*ptr++ = i;
		}

		/* Abort if ctrl-c was pressed */
		if (ctrlc()) {
			puts("\nAbort\n");
			return 0;
		}
		putc('.');
	}
	return 0;
}

U_BOOT_CMD(writepci, 3, 1, do_writepci,
	   "writepci- Write some data to pcibus\n",
	   "<addr> <size>\n" "        - Write some data to pcibus.\n");
Commit	Line	Data
5e4b3361 SR	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* pf5200.c - main board support/init for the esd pf5200.
	29	*/
	30
	31	#include <common.h>
	32	#include <mpc5xxx.h>
	33	#include <pci.h>
	34	#include <command.h>
	35
	36	#include "mt46v16m16-75.h"
	37
	38	void init_power_switch(void);
	39
	40	static void sdram_start(int hi_addr)
	41	{
	42	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	43
	44	/* unlock mode register */
	45	(vu_long ) MPC5XXX_SDRAM_CTRL =
	46	SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	47	__asm__ volatile ("sync");
	48
	49	/* precharge all banks */
	50	(vu_long ) MPC5XXX_SDRAM_CTRL =
	51	SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	52	__asm__ volatile ("sync");
	53
	54	/* set mode register: extended mode */
	55	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	56	__asm__ volatile ("sync");
	57
	58	/* set mode register: reset DLL */
	59	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	60	__asm__ volatile ("sync");
	61
	62	/* precharge all banks */
	63	(vu_long ) MPC5XXX_SDRAM_CTRL =
	64	SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
65	__asm__ volatile ("sync");
66
67	/* auto refresh */
68	(vu_long ) MPC5XXX_SDRAM_CTRL =
69	SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
70	__asm__ volatile ("sync");
71
72	/* set mode register */
73	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
74	__asm__ volatile ("sync");
75
76	/* normal operation */
77	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
78	__asm__ volatile ("sync");
79	}
80
81	/*
82	* ATTENTION: Although partially referenced initdram does NOT make real use
83	* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
84	* is something else than 0x00000000.
85	*/
86
87	long int initdram(int board_type)
88	{
89	ulong dramsize = 0;
90	ulong test1, test2;
91
92	/* setup SDRAM chip selects */
93	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
94	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
95	__asm__ volatile ("sync");
96
97	/* setup config registers */
98	(vu_long ) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
99	(vu_long ) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
100	__asm__ volatile ("sync");
101
102	/* set tap delay */
103	(vu_long ) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
104	__asm__ volatile ("sync");
105
106	/* find RAM size using SDRAM CS0 only */
107	sdram_start(0);
77ddac94	108	test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
5e4b3361	109	sdram_start(1);
77ddac94	110	test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
5e4b3361 SR	111
	112	if (test1 > test2) {
	113	sdram_start(0);
	114	dramsize = test1;
	115	} else {
	116	dramsize = test2;
	117	}
	118
	119	/* memory smaller than 1MB is impossible */
	120	if (dramsize < (1 << 20)) {
	121	dramsize = 0;
	122	}
	123
	124	/* set SDRAM CS0 size according to the amount of RAM found */
	125	if (dramsize > 0) {
	126	(vu_long ) MPC5XXX_SDRAM_CS0CFG =
	127	0x13 + __builtin_ffs(dramsize >> 20) - 1;
	128	/* let SDRAM CS1 start right after CS0 */
	129	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
	130	} else {
	131	#if 0
	132	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	133	/* let SDRAM CS1 start right after CS0 */
	134	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
	135	#else
	136	(vu_long ) MPC5XXX_SDRAM_CS0CFG =
	137	0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
	138	/* let SDRAM CS1 start right after CS0 */
	139	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
	140	#endif
	141	}
	142
	143	#if 0
	144	/* find RAM size using SDRAM CS1 only */
	145	sdram_start(0);
	146	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
	147	sdram_start(1);
	148	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
	149	sdram_start(0);
	150	#endif
	151	/* set SDRAM CS1 size according to the amount of RAM found */
	152
	153	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	154
	155	init_power_switch();
	156	return (dramsize);
	157	}
	158
	159	int checkboard(void)
	160	{
	161	puts("Board: esd ParaFinder (pf5200)\n");
	162	return 0;
	163	}
	164
	165	void flash_preinit(void)
	166	{
	167	/*
	168	* Now, when we are in RAM, enable flash write
	169	* access for detection process.
	170	* Note that CS_BOOT cannot be cleared when
	171	* executing in flash.
	172	*/
	173	(vu_long ) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	174	}
175
176	void flash_afterinit(ulong size)
177	{
178	if (size == 0x02000000) {
179	/* adjust mapping */
180	(vu_long ) MPC5XXX_BOOTCS_START =
181	(vu_long ) MPC5XXX_CS0_START =
182	START_REG(CFG_BOOTCS_START \| size);
183	(vu_long ) MPC5XXX_BOOTCS_STOP =
184	(vu_long ) MPC5XXX_CS0_STOP =
185	STOP_REG(CFG_BOOTCS_START \| size, size);
186	}
187	}
188
189	#ifdef CONFIG_PCI
190	static struct pci_controller hose;
191
192	extern void pci_mpc5xxx_init(struct pci_controller *);
193
dd520bf3	194	void pci_init_board(void) {
5e4b3361 SR	195	pci_mpc5xxx_init(&hose);
	196	}
	197	#endif
	198
77a31854	199	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
5e4b3361	200
5e4b3361 SR	201	void init_ide_reset(void)
	202	{
	203	debug("init_ide_reset\n");
	204
	205	/* Configure PSC1_4 as GPIO output for ATA reset */
	206	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	207	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	208	}
	209
	210	void ide_set_reset(int idereset)
	211	{
	212	debug("ide_reset(%d)\n", idereset);
	213
	214	if (idereset) {
dae80f3c	215	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
5e4b3361	216	} else {
dae80f3c	217	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
5e4b3361 SR	218	}
5e4b3361 SR	219	}
77a31854	220	#endif
5e4b3361 SR	221
	222	#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
	223	#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
	224	#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
	225	#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
	226
	227	#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
	228	#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
	229	#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
	230	#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
	231
	232	#define GPIO_WU6 0x40000000UL
	233	#define GPIO_USB0 0x00010000UL
	234	#define GPIO_USB9 0x08000000UL
	235	#define GPIO_USB9S 0x00080000UL
	236
	237	void init_power_switch(void)
	238	{
	239	debug("init_power_switch\n");
	240
	241	/* Configure GPIO_WU6 as GPIO output for ATA reset */
dae80f3c	242	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_WU6;
5e4b3361 SR	243	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_WU6;
	244	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_WU6;
	245	__asm__ volatile ("sync");
	246
	247	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
	248	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_ENABLE \|= GPIO_USB0;
	249	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DIR \|= GPIO_USB0;
	250	__asm__ volatile ("sync");
	251
	252	(vu_long ) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
	253	(vu_long ) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
	254	__asm__ volatile ("sync");
	255
	256	if (((vu_long ) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
	257	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT \|= GPIO_USB0;
	258	__asm__ volatile ("sync");
	259	}
	260	(vu_char ) CFG_CS1_START = 0x02; /* Red Power LED on */
	261	__asm__ volatile ("sync");
	262
	263	(vu_char ) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
	264	__asm__ volatile ("sync");
	265	}
	266
	267	void power_set_reset(int power)
	268	{
	269	debug("ide_set_reset(%d)\n", power);
	270
	271	if (power) {
dae80f3c	272	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
5e4b3361 SR	273	(vu_long ) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
5e4b3361 SR	274	} else {
dae80f3c	275	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_WU6;
5e4b3361 SR	276	if (((vu_long ) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
	277	0) {
	278	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT \|=
	279	GPIO_USB0;
	280	}
	281
	282	}
	283	}
	284
	285	int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	286	{
	287	power_set_reset(1);
	288	return (0);
	289	}
	290
	291	U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL);
	292
	293	int phypower(int flag)
	294	{
	295	u32 addr;
	296	vu_long *reg;
	297	int status;
	298	pci_dev_t dev;
	299
	300	dev = PCI_BDF(0, 0x18, 0);
	301	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
	302	if (status == 0) {
	303	reg = (vu_long *) (addr + 0x00000040);
	304	*reg \|= 0x40000000;
	305	__asm__ volatile ("sync");
	306
	307	reg = (vu_long *) (addr + 0x001000c);
	308	*reg \|= 0x20000000;
	309	__asm__ volatile ("sync");
	310
	311	reg = (vu_long *) (addr + 0x0010004);
	312	if (flag != 0) {
	313	*reg &= ~0x20000000;
	314	} else {
	315	*reg \|= 0x20000000;
	316	}
	317	__asm__ volatile ("sync");
	318	}
	319	return (status);
	320	}
	321
	322	int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	323	{
	324	int status;
	325
	326	if (argv[1][0] == '0') {
	327	status = phypower(0);
	328	} else {
	329	status = phypower(1);
	330	}
	331	return (0);
	332	}
	333
	334	U_BOOT_CMD(phypower, 2, 2, do_phypower,
	335	"phypower- Switch power of ethernet phy\n", NULL);
	336
	337	int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	338	{
	339	unsigned int addr;
340	unsigned int size;
341	int i;
342	volatile unsigned long *ptr;
343
344	addr = simple_strtol(argv[1], NULL, 16);
345	size = simple_strtol(argv[2], NULL, 16);
346
347	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
348
349	while (1) {
350	ptr = (volatile unsigned long *)addr;
351	for (i = 0; i < (size >> 2); i++) {
352	*ptr++ = i;
353	}
354
355	/* Abort if ctrl-c was pressed */
356	if (ctrlc()) {
357	puts("\nAbort\n");
358	return 0;
359	}
360	putc('.');
361	}
362	return 0;
363	}
364
365	U_BOOT_CMD(writepci, 3, 1, do_writepci,
366	"writepci- Write some data to pcibus\n",
367	"<addr> <size>\n" " - Write some data to pcibus.\n");