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72c5d52a | 1 | /* |
1a459660 | 2 | * SPDX-License-Identifier: GPL-2.0+ |
72c5d52a MF |
3 | */ |
4 | ||
25ddd1fb | 5 | #include <asm-offsets.h> |
72c5d52a | 6 | #include <ppc_asm.tmpl> |
61f2b38a | 7 | #include <asm/mmu.h> |
72c5d52a MF |
8 | #include <config.h> |
9 | ||
3b4bd2d7 | 10 | /* |
72c5d52a MF |
11 | * TLB TABLE |
12 | * | |
13 | * This table is used by the cpu boot code to setup the initial tlb | |
14 | * entries. Rather than make broad assumptions in the cpu source tree, | |
15 | * this table lets each board set things up however they like. | |
16 | * | |
17 | * Pointer to the table is returned in r1 | |
18 | * | |
3b4bd2d7 | 19 | */ |
72c5d52a MF |
20 | .section .bootpg,"ax" |
21 | .globl tlbtab | |
22 | ||
23 | tlbtab: | |
24 | tlbtab_start | |
25 | ||
26 | /* | |
27 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
28 | * speed up boot process. It is patched after relocation to enable SA_I | |
29 | */ | |
30 | #ifndef CONFIG_NAND_SPL | |
cf6eb6da | 31 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) |
72c5d52a | 32 | #else |
cf6eb6da | 33 | tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) |
72c5d52a MF |
34 | #endif |
35 | ||
3b4bd2d7 | 36 | /* TLB entries for DDR2 SDRAM are generated dynamically */ |
72c5d52a | 37 | |
6d0f6bcf | 38 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
72c5d52a | 39 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
cf6eb6da | 40 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
72c5d52a MF |
41 | #endif |
42 | ||
43 | /* TLB-entry for PCI Memory */ | |
cf6eb6da SR |
44 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) |
45 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) | |
46 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) | |
47 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) | |
72c5d52a MF |
48 | |
49 | /* TLB-entries for EBC */ | |
50 | /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral | |
51 | * tlb entry. | |
52 | * This dummy entry is only for convinience in order not to modify the | |
53 | * amount of entries. Currently OS/9 relies on this :-) | |
54 | */ | |
cf6eb6da | 55 | tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG ) |
72c5d52a MF |
56 | |
57 | /* TLB-entry for NAND */ | |
cf6eb6da | 58 | tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) |
72c5d52a MF |
59 | |
60 | /* TLB-entry for Internal Registers & OCM */ | |
cf6eb6da | 61 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) |
72c5d52a MF |
62 | |
63 | /*TLB-entry PCI registers*/ | |
cf6eb6da | 64 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) |
72c5d52a MF |
65 | |
66 | /* TLB-entry for peripherals */ | |
cf6eb6da | 67 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
72c5d52a MF |
68 | |
69 | /* TLB-entry PCI IO space */ | |
cf6eb6da | 70 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) |
72c5d52a MF |
71 | |
72 | /* TODO: what about high IO space */ | |
73 | tlbtab_end | |
74 | ||
75 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
76 | /* | |
77 | * For NAND booting the first TLB has to be reconfigured to full size | |
78 | * and with caching disabled after running from RAM! | |
79 | */ | |
6d0f6bcf JCPV |
80 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
81 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) | |
cf6eb6da | 82 | #define TLB02 TLB2(AC_RWX | SA_IG) |
72c5d52a MF |
83 | |
84 | .globl reconfig_tlb0 | |
85 | reconfig_tlb0: | |
86 | sync | |
87 | isync | |
88 | addi r4,r0,0x0000 /* TLB entry #0 */ | |
89 | lis r5,TLB00@h | |
90 | ori r5,r5,TLB00@l | |
91 | tlbwe r5,r4,0x0000 /* Save it out */ | |
92 | lis r5,TLB01@h | |
93 | ori r5,r5,TLB01@l | |
94 | tlbwe r5,r4,0x0001 /* Save it out */ | |
95 | lis r5,TLB02@h | |
96 | ori r5,r5,TLB02@l | |
97 | tlbwe r5,r4,0x0002 /* Save it out */ | |
98 | sync | |
99 | isync | |
100 | blr | |
101 | #endif |