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72c5d52a MF |
1 | /* |
2 | * | |
3 | * See file CREDITS for list of people who contributed to this | |
4 | * project. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <ppc_asm.tmpl> | |
23 | #include <asm-ppc/mmu.h> | |
24 | #include <config.h> | |
25 | ||
26 | /************************************************************************** | |
27 | * TLB TABLE | |
28 | * | |
29 | * This table is used by the cpu boot code to setup the initial tlb | |
30 | * entries. Rather than make broad assumptions in the cpu source tree, | |
31 | * this table lets each board set things up however they like. | |
32 | * | |
33 | * Pointer to the table is returned in r1 | |
34 | * | |
35 | *************************************************************************/ | |
36 | .section .bootpg,"ax" | |
37 | .globl tlbtab | |
38 | ||
39 | tlbtab: | |
40 | tlbtab_start | |
41 | ||
42 | /* | |
43 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
44 | * speed up boot process. It is patched after relocation to enable SA_I | |
45 | */ | |
46 | #ifndef CONFIG_NAND_SPL | |
6d0f6bcf | 47 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) |
72c5d52a | 48 | #else |
6d0f6bcf | 49 | tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) |
72c5d52a MF |
50 | #endif |
51 | ||
52 | /* TLB-entry for DDR SDRAM (Up to 2GB) */ | |
53 | #ifdef CONFIG_4xx_DCACHE | |
6d0f6bcf | 54 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) |
72c5d52a | 55 | #else |
6d0f6bcf | 56 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
72c5d52a MF |
57 | #endif |
58 | ||
6d0f6bcf | 59 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
72c5d52a | 60 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
6d0f6bcf | 61 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) |
72c5d52a MF |
62 | #endif |
63 | ||
64 | /* TLB-entry for PCI Memory */ | |
6d0f6bcf JCPV |
65 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) |
66 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) | |
67 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) | |
68 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) | |
72c5d52a MF |
69 | |
70 | /* TLB-entries for EBC */ | |
71 | /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral | |
72 | * tlb entry. | |
73 | * This dummy entry is only for convinience in order not to modify the | |
74 | * amount of entries. Currently OS/9 relies on this :-) | |
75 | */ | |
76 | tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
77 | ||
78 | /* TLB-entry for NAND */ | |
6d0f6bcf | 79 | tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
72c5d52a MF |
80 | |
81 | /* TLB-entry for Internal Registers & OCM */ | |
82 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) | |
83 | ||
84 | /*TLB-entry PCI registers*/ | |
85 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
86 | ||
87 | /* TLB-entry for peripherals */ | |
88 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) | |
89 | ||
90 | /* TLB-entry PCI IO space */ | |
91 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) | |
92 | ||
93 | /* TODO: what about high IO space */ | |
94 | tlbtab_end | |
95 | ||
96 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
97 | /* | |
98 | * For NAND booting the first TLB has to be reconfigured to full size | |
99 | * and with caching disabled after running from RAM! | |
100 | */ | |
6d0f6bcf JCPV |
101 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
102 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) | |
72c5d52a MF |
103 | #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) |
104 | ||
105 | .globl reconfig_tlb0 | |
106 | reconfig_tlb0: | |
107 | sync | |
108 | isync | |
109 | addi r4,r0,0x0000 /* TLB entry #0 */ | |
110 | lis r5,TLB00@h | |
111 | ori r5,r5,TLB00@l | |
112 | tlbwe r5,r4,0x0000 /* Save it out */ | |
113 | lis r5,TLB01@h | |
114 | ori r5,r5,TLB01@l | |
115 | tlbwe r5,r4,0x0001 /* Save it out */ | |
116 | lis r5,TLB02@h | |
117 | ori r5,r5,TLB02@l | |
118 | tlbwe r5,r4,0x0002 /* Save it out */ | |
119 | sync | |
120 | isync | |
121 | blr | |
122 | #endif |