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15647dc7 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc824x.h> | |
26 | #include <pci.h> | |
7abf0c58 | 27 | #include <i2c.h> |
10efa024 | 28 | #include <netdev.h> |
15647dc7 | 29 | |
d87080b7 WD |
30 | DECLARE_GLOBAL_DATA_PTR; |
31 | ||
15647dc7 WD |
32 | int checkboard (void) |
33 | { | |
34 | /*TODO: Check processor type */ | |
35 | ||
36 | puts ( "Board: Debris " | |
37 | #ifdef CONFIG_MPC8240 | |
38 | "8240" | |
39 | #endif | |
40 | #ifdef CONFIG_MPC8245 | |
41 | "8245" | |
42 | #endif | |
43 | " ##Test not implemented yet##\n"); | |
44 | return 0; | |
45 | } | |
46 | ||
53677ef1 | 47 | #if 0 /* NOT USED */ |
15647dc7 WD |
48 | int checkflash (void) |
49 | { | |
50 | /* TODO: XXX XXX XXX */ | |
51 | printf ("## Test not implemented yet ##\n"); | |
52 | ||
53 | return (0); | |
54 | } | |
55 | #endif | |
56 | ||
9973e3c6 | 57 | phys_size_t initdram (int board_type) |
15647dc7 | 58 | { |
7abf0c58 WD |
59 | int m, row, col, bank, i; |
60 | unsigned long start, end; | |
61 | uint32_t mccr1; | |
62 | uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; | |
63 | uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; | |
64 | uint8_t mber = 0; | |
15647dc7 | 65 | |
6d0f6bcf | 66 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
15647dc7 | 67 | |
7abf0c58 WD |
68 | if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ |
69 | m = i2c_reg_read (0x50, 5); /* # of physical banks */ | |
70 | row = i2c_reg_read (0x50, 3); /* # of rows */ | |
71 | col = i2c_reg_read (0x50, 4); /* # of columns */ | |
72 | bank = i2c_reg_read (0x50, 17); /* # of logical banks */ | |
73 | ||
74 | CONFIG_READ_WORD(MCCR1, mccr1); | |
75 | mccr1 &= 0xffff0000; | |
76 | ||
6d0f6bcf | 77 | start = CONFIG_SYS_SDRAM_BASE; |
7abf0c58 WD |
78 | end = start + (1 << (col + row + 3) ) * bank - 1; |
79 | ||
80 | for (i = 0; i < m; i++) { | |
81 | mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; | |
82 | if (i < 4) { | |
83 | msar1 |= ((start >> 20) & 0xff) << i * 8; | |
84 | emsar1 |= ((start >> 28) & 0xff) << i * 8; | |
85 | mear1 |= ((end >> 20) & 0xff) << i * 8; | |
86 | emear1 |= ((end >> 28) & 0xff) << i * 8; | |
87 | } else { | |
88 | msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; | |
89 | emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; | |
90 | mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; | |
91 | emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; | |
92 | } | |
93 | mber |= 1 << i; | |
94 | start += (1 << (col + row + 3) ) * bank; | |
95 | end += (1 << (col + row + 3) ) * bank; | |
96 | } | |
97 | for (; i < 8; i++) { | |
98 | if (i < 4) { | |
99 | msar1 |= 0xff << i * 8; | |
100 | emsar1 |= 0x30 << i * 8; | |
101 | mear1 |= 0xff << i * 8; | |
102 | emear1 |= 0x30 << i * 8; | |
103 | } else { | |
104 | msar2 |= 0xff << (i-4) * 8; | |
105 | emsar2 |= 0x30 << (i-4) * 8; | |
106 | mear2 |= 0xff << (i-4) * 8; | |
107 | emear2 |= 0x30 << (i-4) * 8; | |
108 | } | |
109 | } | |
110 | ||
111 | CONFIG_WRITE_WORD(MCCR1, mccr1); | |
112 | CONFIG_WRITE_WORD(MSAR1, msar1); | |
113 | CONFIG_WRITE_WORD(EMSAR1, emsar1); | |
114 | CONFIG_WRITE_WORD(MEAR1, mear1); | |
115 | CONFIG_WRITE_WORD(EMEAR1, emear1); | |
116 | CONFIG_WRITE_WORD(MSAR2, msar2); | |
117 | CONFIG_WRITE_WORD(EMSAR2, emsar2); | |
118 | CONFIG_WRITE_WORD(MEAR2, mear2); | |
119 | CONFIG_WRITE_WORD(EMEAR2, emear2); | |
120 | CONFIG_WRITE_BYTE(MBER, mber); | |
15647dc7 | 121 | |
7abf0c58 | 122 | return (1 << (col + row + 3) ) * bank * m; |
15647dc7 WD |
123 | } |
124 | ||
125 | /* | |
126 | * Initialize PCI Devices, report devices found. | |
127 | */ | |
128 | #ifndef CONFIG_PCI_PNP | |
129 | static struct pci_config_table pci_debris_config_table[] = { | |
130 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, | |
131 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, | |
132 | PCI_ENET0_MEMADDR, | |
133 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, | |
134 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, | |
135 | pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, | |
136 | PCI_ENET1_MEMADDR, | |
137 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, | |
138 | { } | |
139 | }; | |
140 | #endif | |
141 | ||
142 | struct pci_controller hose = { | |
143 | #ifndef CONFIG_PCI_PNP | |
144 | config_table: pci_debris_config_table, | |
145 | #endif | |
146 | }; | |
147 | ||
148 | void pci_init_board(void) | |
149 | { | |
150 | pci_mpc824x_init(&hose); | |
151 | } | |
152 | ||
153 | void *nvram_read(void *dest, const long src, size_t count) | |
154 | { | |
155 | volatile uchar *d = (volatile uchar*) dest; | |
156 | volatile uchar *s = (volatile uchar*) src; | |
157 | while(count--) { | |
158 | *d++ = *s++; | |
159 | asm volatile("sync"); | |
160 | } | |
161 | return dest; | |
162 | } | |
163 | ||
164 | void nvram_write(long dest, const void *src, size_t count) | |
165 | { | |
166 | volatile uchar *d = (volatile uchar*)dest; | |
167 | volatile uchar *s = (volatile uchar*)src; | |
168 | while(count--) { | |
169 | *d++ = *s++; | |
170 | asm volatile("sync"); | |
171 | } | |
172 | } | |
173 | ||
174 | int misc_init_r(void) | |
175 | { | |
15647dc7 | 176 | /* Write ethernet addr in NVRAM for VxWorks */ |
6d0f6bcf | 177 | nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS, |
15647dc7 WD |
178 | (char*)&gd->bd->bi_enetaddr[0], 6); |
179 | return 0; | |
180 | } | |
10efa024 BW |
181 | |
182 | int board_eth_init(bd_t *bis) | |
183 | { | |
184 | return pci_eth_init(bis); | |
185 | } |