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1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc824x.h> | |
26 | #include <pci.h> | |
27 | #include <i2c.h> | |
28 | #include <asm/processor.h> | |
29 | ||
30 | int checkboard(void) | |
31 | { | |
32 | puts ("Board: KVME080\n"); | |
33 | return 0; | |
34 | } | |
35 | ||
36 | unsigned long setdram(int m, int row, int col, int bank) | |
37 | { | |
38 | int i; | |
39 | unsigned long start, end; | |
40 | uint32_t mccr1; | |
41 | uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; | |
42 | uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; | |
43 | uint8_t mber = 0; | |
44 | ||
45 | CONFIG_READ_WORD(MCCR1, mccr1); | |
46 | mccr1 &= 0xffff0000; | |
47 | ||
48 | start = CFG_SDRAM_BASE; | |
49 | end = start + (1 << (col + row + 3) ) * bank - 1; | |
50 | ||
51 | for (i = 0; i < m; i++) { | |
52 | mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; | |
53 | if (i < 4) { | |
54 | msar1 |= ((start >> 20) & 0xff) << i * 8; | |
55 | emsar1 |= ((start >> 28) & 0xff) << i * 8; | |
56 | mear1 |= ((end >> 20) & 0xff) << i * 8; | |
57 | emear1 |= ((end >> 28) & 0xff) << i * 8; | |
58 | } else { | |
59 | msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; | |
60 | emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; | |
61 | mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; | |
62 | emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; | |
63 | } | |
64 | mber |= 1 << i; | |
65 | start += (1 << (col + row + 3) ) * bank; | |
66 | end += (1 << (col + row + 3) ) * bank; | |
67 | } | |
68 | for (; i < 8; i++) { | |
69 | if (i < 4) { | |
70 | msar1 |= 0xff << i * 8; | |
71 | emsar1 |= 0x30 << i * 8; | |
72 | mear1 |= 0xff << i * 8; | |
73 | emear1 |= 0x30 << i * 8; | |
74 | } else { | |
75 | msar2 |= 0xff << (i-4) * 8; | |
76 | emsar2 |= 0x30 << (i-4) * 8; | |
77 | mear2 |= 0xff << (i-4) * 8; | |
78 | emear2 |= 0x30 << (i-4) * 8; | |
79 | } | |
80 | } | |
81 | ||
82 | CONFIG_WRITE_WORD(MCCR1, mccr1); | |
83 | CONFIG_WRITE_WORD(MSAR1, msar1); | |
84 | CONFIG_WRITE_WORD(EMSAR1, emsar1); | |
85 | CONFIG_WRITE_WORD(MEAR1, mear1); | |
86 | CONFIG_WRITE_WORD(EMEAR1, emear1); | |
87 | CONFIG_WRITE_WORD(MSAR2, msar2); | |
88 | CONFIG_WRITE_WORD(EMSAR2, emsar2); | |
89 | CONFIG_WRITE_WORD(MEAR2, mear2); | |
90 | CONFIG_WRITE_WORD(EMEAR2, emear2); | |
91 | CONFIG_WRITE_BYTE(MBER, mber); | |
92 | ||
93 | return (1 << (col + row + 3) ) * bank * m; | |
94 | } | |
95 | ||
9973e3c6 | 96 | phys_size_t initdram(int board_type) |
53dd6ce4 WD |
97 | { |
98 | unsigned int msr; | |
99 | long int size = 0; | |
100 | ||
101 | msr = mfmsr(); | |
102 | mtmsr(msr & ~(MSR_IR | MSR_DR)); | |
103 | mtspr(IBAT2L, CFG_IBAT0L + 0x10000000); | |
104 | mtspr(IBAT2U, CFG_IBAT0U + 0x10000000); | |
105 | mtspr(DBAT2L, CFG_DBAT0L + 0x10000000); | |
106 | mtspr(DBAT2U, CFG_DBAT0U + 0x10000000); | |
107 | mtmsr(msr); | |
108 | ||
109 | if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000)) | |
110 | size = 0x20000000; /* 512MB */ | |
111 | else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000)) | |
112 | size = 0x10000000; /* 256MB */ | |
113 | else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000)) | |
114 | size = 0x10000000; /* 256MB */ | |
115 | else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000)) | |
116 | size = 0x08000000; /* 128MB */ | |
117 | else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000)) | |
118 | size = 0x08000000; /* 128MB */ | |
119 | else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000)) | |
120 | size = 0x04000000; /* 64MB */ | |
121 | ||
122 | msr = mfmsr(); | |
123 | mtmsr(msr & ~(MSR_IR | MSR_DR)); | |
124 | mtspr(IBAT2L, CFG_IBAT2L); | |
125 | mtspr(IBAT2U, CFG_IBAT2U); | |
126 | mtspr(DBAT2L, CFG_DBAT2L); | |
127 | mtspr(DBAT2U, CFG_DBAT2U); | |
128 | mtmsr(msr); | |
129 | ||
130 | return size; | |
131 | } | |
132 | ||
133 | struct pci_controller hose; | |
134 | ||
135 | void pci_init_board(void) | |
136 | { | |
137 | pci_mpc824x_init(&hose); | |
138 | } | |
139 | ||
140 | int board_early_init_f(void) | |
141 | { | |
142 | *(volatile unsigned char *)(0xff080120) = 0xfb; | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | int board_early_init_r(void) | |
148 | { | |
149 | unsigned int msr; | |
150 | ||
151 | CONFIG_WRITE_WORD(ERCR1, 0x95ff8000); | |
152 | CONFIG_WRITE_WORD(ERCR3, 0x0c00000e); | |
153 | CONFIG_WRITE_WORD(ERCR4, 0x0800000e); | |
154 | ||
155 | msr = mfmsr(); | |
156 | mtmsr(msr & ~(MSR_IR | MSR_DR)); | |
157 | mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); | |
158 | mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); | |
159 | mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); | |
160 | mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); | |
161 | mtmsr(msr); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | extern int multiverse_init(void); | |
167 | ||
168 | int misc_init_r(void) | |
169 | { | |
170 | multiverse_init(); | |
171 | return 0; | |
172 | } | |
173 | ||
174 | void *nvram_read(void *dest, const long src, size_t count) | |
175 | { | |
176 | volatile uchar *d = (volatile uchar*) dest; | |
177 | volatile uchar *s = (volatile uchar*) src; | |
178 | while(count--) { | |
179 | *d++ = *s++; | |
180 | asm volatile("sync"); | |
181 | } | |
182 | return dest; | |
183 | } | |
184 | ||
185 | void nvram_write(long dest, const void *src, size_t count) | |
186 | { | |
187 | volatile uchar *d = (volatile uchar*)dest; | |
188 | volatile uchar *s = (volatile uchar*)src; | |
189 | while(count--) { | |
190 | *d++ = *s++; | |
191 | asm volatile("sync"); | |
192 | } | |
193 | } |