projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 53dd6ce4 WD |
1 | /* |
| 2 | * multiverse.h | |
| 3 | * | |
| 4 | * VME driver for Multiverse | |
| 5 | * | |
| 6 | * Author : Sangmoon Kim | |
| 7 | * dogoil@etinsys.com | |
| 8 | * | |
| 9 | * Copyright 2005 ETIN SYSTEMS Co.,Ltd. | |
| 10 | * | |
| 1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
| 53dd6ce4 WD |
12 | */ |
| 13 | ||
| 14 | #ifndef __MULTIVERSE_H__ | |
| 15 | #define __MULTIVERSE_H__ | |
| 16 | ||
| 17 | #define VME_A32_MSTR_BUS 0x90000000 | |
| 18 | #define VME_A32_MSTR_SIZE 0x01000000 | |
| 19 | ||
| 20 | #define VME_A32_SLV_SIZE 0x01000000 | |
| 21 | ||
| 22 | #define VME_A32_SLV_BUS 0x90000000 | |
| 23 | #define VME_A24_SLV_BUS 0x00000000 | |
| 24 | #define VME_A16_SLV_BUS 0x00000000 | |
| 25 | ||
| 26 | #define VME_A32_SLV_LOCAL 0x00000000 | |
| 27 | #define VME_A24_SLV_LOCAL 0x00000000 | |
| 28 | #define VME_A16_SLV_LOCAL 0x00000000 | |
| 29 | ||
| 30 | #define A32_SLV_WINDOW | |
| 31 | #undef A24_SLV_WINDOW | |
| 32 | #undef A16_SLV_WINDOW | |
| 33 | #undef REG_SLV_WINDOW | |
| 34 | ||
| 35 | /* PCI Registers */ | |
| 36 | ||
| 37 | #define P_IMG_CTRL0 0x100 | |
| 38 | #define P_BA0 0x104 | |
| 39 | #define P_AM0 0x108 | |
| 40 | #define P_TA0 0x10C | |
| 41 | #define P_IMG_CTRL1 0x110 | |
| 42 | #define P_BA1 0x114 | |
| 43 | #define P_AM1 0x118 | |
| 44 | #define P_TA1 0x11C | |
| 45 | #define P_IMG_CTRL2 0x120 | |
| 46 | #define P_BA2 0x124 | |
| 47 | #define P_AM2 0x128 | |
| 48 | #define P_TA2 0x12C | |
| 49 | #define P_IMG_CTRL3 0x130 | |
| 50 | #define P_BA3 0x134 | |
| 51 | #define P_AM3 0x138 | |
| 52 | #define P_TA3 0x13C | |
| 53 | #define P_IMG_CTRL4 0x140 | |
| 54 | #define P_BA4 0x144 | |
| 55 | #define P_AM4 0x148 | |
| 56 | #define P_TA4 0x14C | |
| 57 | #define P_IMG_CTRL5 0x150 | |
| 58 | #define P_BA5 0x154 | |
| 59 | #define P_AM5 0x158 | |
| 60 | #define P_TA5 0x15C | |
| 61 | #define P_ERR_CS 0x160 | |
| 62 | #define P_ERR_ADDR 0x164 | |
| 63 | #define P_ERR_DATA 0x168 | |
| 64 | ||
| 65 | #define WB_CONF_SPC_BAR 0x180 | |
| 66 | #define W_IMG_CTRL1 0x184 | |
| 67 | #define W_BA1 0x188 | |
| 68 | #define W_AM1 0x18C | |
| 69 | #define W_TA1 0x190 | |
| 70 | #define W_IMG_CTRL2 0x194 | |
| 71 | #define W_BA2 0x198 | |
| 72 | #define W_AM2 0x19C | |
| 73 | #define W_TA2 0x1A0 | |
| 74 | #define W_IMG_CTRL3 0x1A4 | |
| 75 | #define W_BA3 0x1A8 | |
| 76 | #define W_AM3 0x1AC | |
| 77 | #define W_TA3 0x1B0 | |
| 78 | #define W_IMG_CTRL4 0x1B4 | |
| 79 | #define W_BA4 0x1B8 | |
| 80 | #define W_AM4 0x1BC | |
| 81 | #define W_TA4 0x1C0 | |
| 82 | #define W_IMG_CTRL5 0x1C4 | |
| 83 | #define W_BA5 0x1C8 | |
| 84 | #define W_AM5 0x1CC | |
| 85 | #define W_TA5 0x1D0 | |
| 86 | #define W_ERR_CS 0x1D4 | |
| 87 | #define W_ERR_ADDR 0x1D8 | |
| 88 | #define W_ERR_DATA 0x1DC | |
| 89 | #define CNF_ADDR 0x1E0 | |
| 90 | #define CNF_DATA 0x1E4 | |
| 91 | #define INT_ACK 0x1E8 | |
| 92 | #define ICR 0x1EC | |
| 93 | #define ISR 0x1F0 | |
| 94 | ||
| 95 | /* VME registers */ | |
| 96 | ||
| 97 | #define VME_SLAVE32_AM 0x03 | |
| 98 | #define VME_SLAVE24_AM 0x02 | |
| 99 | #define VME_SLAVE16_AM 0x01 | |
| 100 | #define VME_SLAVE_REG_AM 0x00 | |
| 101 | #define VME_SLAVE32_A 0x07 | |
| 102 | #define VME_SLAVE24_A 0x06 | |
| 103 | #define VME_SLAVE16_A 0x05 | |
| 104 | #define VME_SLAVE_REG_A 0x04 | |
| 105 | #define VME_SLAVE32_MASK 0x0B | |
| 106 | #define VME_SLAVE24_MASK 0x0A | |
| 107 | #define VME_SLAVE16_MASK 0x09 | |
| 108 | #define VME_SLAVE_REG_MASK 0x08 | |
| 109 | #define VME_SLAVE32_EN 0x0F | |
| 110 | #define VME_SLAVE24_EN 0x0E | |
| 111 | #define VME_SLAVE16_EN 0x0D | |
| 112 | #define VME_SLAVE_REG_EN 0x0C | |
| 113 | #define VME_MASTER32_AM 0x13 | |
| 114 | #define VME_MASTER24_AM 0x12 | |
| 115 | #define VME_MASTER16_AM 0x11 | |
| 116 | #define VME_MASTER_REG_AM 0x10 | |
| 117 | #define VME_RMW_ADRS 0x14 | |
| 118 | #define VME_MBOX 0x18 | |
| 119 | #define VME_STATUS 0x1E | |
| 120 | #define VME_CTRL 0x1C | |
| 121 | #define VME_IRQ 0x20 | |
| 122 | #define VME_INT_EN 0x21 | |
| 123 | #define VME_INT 0x22 | |
| 124 | #define VME_IRQ1_REG 0x24 | |
| 125 | #define VME_IRQ2_REG 0x28 | |
| 126 | #define VME_IRQ3_REG 0x2C | |
| 127 | #define VME_IRQ4_REG 0x30 | |
| 128 | #define VME_IRQ5_REG 0x34 | |
| 129 | #define VME_IRQ6_REG 0x38 | |
| 130 | #define VME_IRQ7_REG 0x3C | |
| 131 | ||
| 132 | /* VME control register */ | |
| 133 | ||
| 134 | #define VME_CTRL_BRDRST 0x01 | |
| 135 | #define VME_CTRL_SYSRST 0x02 | |
| 136 | #define VME_CTRL_RMW 0x04 | |
| 137 | #define VME_CTRL_SHORT_D 0x08 | |
| 138 | #define VME_CTRL_SYSFAIL 0x10 | |
| 139 | #define VME_CTRL_VOWN 0x20 | |
| 140 | #define VME_CTRL_A16_REG_MODE 0x40 | |
| 141 | ||
| 142 | /* VME status register */ | |
| 143 | ||
| 144 | #define VME_STATUS_SYSCON 0x01 | |
| 145 | #define VME_STATUS_SYSFAIL 0x02 | |
| 146 | #define VME_STATUS_ACFAIL 0x04 | |
| 147 | #define VME_STATUS_SYSRST 0x08 | |
| 148 | #define VME_STATUS_VOWN 0x10 | |
| 149 | ||
| 150 | /* Interrupt types */ | |
| 151 | ||
| 152 | #define LVL1 0x0002 | |
| 153 | #define LVL2 0x0004 | |
| 154 | #define LVL3 0x0008 | |
| 155 | #define LVL4 0x0010 | |
| 156 | #define LVL5 0x0020 | |
| 157 | #define LVL6 0x0040 | |
| 158 | #define LVL7 0x0080 | |
| 159 | #define MULTIVERSE_INTI_INT 0x0100 | |
| 160 | #define MULTIVERSE_WB_INT 0x0200 | |
| 161 | #define MULTIVERSE_PCI_INT 0x0400 | |
| 162 | ||
| 163 | /* interrupt acknowledge */ | |
| 164 | ||
| 165 | #define VME_IACK1 0x04 | |
| 166 | #define VME_IACK2 0x08 | |
| 167 | #define VME_IACK3 0x0c | |
| 168 | #define VME_IACK4 0x10 | |
| 169 | #define VME_IACK5 0x14 | |
| 170 | #define VME_IACK6 0x18 | |
| 171 | #define VME_IACK7 0x1c | |
| 172 | ||
| 173 | #endif /* __MULTIVERSE_H__ */ |