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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* sdram_init.c - automatic memory sizing */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <74xx_7xx.h> | |
28 | #include <galileo/memory.h> | |
29 | #include <galileo/pci.h> | |
30 | #include <galileo/gt64260R.h> | |
31 | #include <net.h> | |
32 | ||
33 | #include "eth.h" | |
34 | #include "mpsc.h" | |
35 | #include "i2c.h" | |
36 | #include "64260.h" | |
37 | ||
d87080b7 WD |
38 | DECLARE_GLOBAL_DATA_PTR; |
39 | ||
c609719b WD |
40 | /* #define DEBUG */ |
41 | #define MAP_PCI | |
42 | ||
43 | #ifdef DEBUG | |
44 | #define DP(x) x | |
45 | #else | |
46 | #define DP(x) | |
47 | #endif | |
48 | ||
49 | #define GB (1 << 30) | |
50 | ||
51 | /* structure to store the relevant information about an sdram bank */ | |
52 | typedef struct sdram_info { | |
53 | uchar drb_size; | |
54 | uchar registered, ecc; | |
55 | uchar tpar; | |
56 | uchar tras_clocks; | |
57 | uchar burst_len; | |
58 | uchar banks, slot; | |
bf9e3b38 | 59 | int size; /* detected size, not from I2C but from dram_size() */ |
c609719b WD |
60 | } sdram_info_t; |
61 | ||
62 | #ifdef DEBUG | |
bf9e3b38 | 63 | void dump_dimm_info (struct sdram_info *d) |
c609719b | 64 | { |
bf9e3b38 WD |
65 | static const char *ecc_legend[] = { "", " Parity", " ECC" }; |
66 | ||
67 | printf ("dimm%s %sDRAM: %dMibytes:\n", | |
68 | ecc_legend[d->ecc], | |
69 | d->registered ? "R" : "", (d->size >> 20)); | |
70 | printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", | |
71 | d->drb_size, d->tpar, d->tras_clocks, d->burst_len, | |
72 | d->banks, d->slot); | |
c609719b WD |
73 | } |
74 | #endif | |
75 | ||
76 | static int | |
bf9e3b38 WD |
77 | memory_map_bank (unsigned int bankNo, |
78 | unsigned int bankBase, unsigned int bankLength) | |
c609719b WD |
79 | { |
80 | #ifdef DEBUG | |
81 | if (bankLength > 0) { | |
bf9e3b38 WD |
82 | printf ("mapping bank %d at %08x - %08x\n", |
83 | bankNo, bankBase, bankBase + bankLength - 1); | |
c609719b | 84 | } else { |
bf9e3b38 | 85 | printf ("unmapping bank %d\n", bankNo); |
c609719b WD |
86 | } |
87 | #endif | |
88 | ||
bf9e3b38 | 89 | memoryMapBank (bankNo, bankBase, bankLength); |
c609719b WD |
90 | |
91 | return 0; | |
92 | } | |
93 | ||
94 | #ifdef MAP_PCI | |
95 | static int | |
bf9e3b38 WD |
96 | memory_map_bank_pci (unsigned int bankNo, |
97 | unsigned int bankBase, unsigned int bankLength) | |
c609719b WD |
98 | { |
99 | PCI_HOST host; | |
bf9e3b38 WD |
100 | |
101 | for (host = PCI_HOST0; host <= PCI_HOST1; host++) { | |
102 | const int features = | |
c609719b WD |
103 | PREFETCH_ENABLE | |
104 | DELAYED_READ_ENABLE | | |
105 | AGGRESSIVE_PREFETCH | | |
106 | READ_LINE_AGGRESSIVE_PREFETCH | | |
107 | READ_MULTI_AGGRESSIVE_PREFETCH | | |
bf9e3b38 | 108 | MAX_BURST_4 | PCI_NO_SWAP; |
c609719b | 109 | |
bf9e3b38 | 110 | pciMapMemoryBank (host, bankNo, bankBase, bankLength); |
c609719b | 111 | |
bf9e3b38 WD |
112 | pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, |
113 | bankLength); | |
c609719b | 114 | |
bf9e3b38 WD |
115 | pciSetRegionFeatures (host, bankNo, features, bankBase, |
116 | bankLength); | |
c609719b WD |
117 | } |
118 | return 0; | |
119 | } | |
120 | #endif | |
121 | ||
122 | /* ------------------------------------------------------------------------- */ | |
123 | ||
124 | /* much of this code is based on (or is) the code in the pip405 port */ | |
125 | /* thanks go to the authors of said port - Josh */ | |
126 | ||
127 | ||
128 | /* | |
129 | * translate ns.ns/10 coding of SPD timing values | |
130 | * into 10 ps unit values | |
131 | */ | |
bf9e3b38 | 132 | static inline unsigned short NS10to10PS (unsigned char spd_byte) |
c609719b WD |
133 | { |
134 | unsigned short ns, ns10; | |
135 | ||
136 | /* isolate upper nibble */ | |
137 | ns = (spd_byte >> 4) & 0x0F; | |
138 | /* isolate lower nibble */ | |
139 | ns10 = (spd_byte & 0x0F); | |
140 | ||
bf9e3b38 | 141 | return (ns * 100 + ns10 * 10); |
c609719b WD |
142 | } |
143 | ||
144 | /* | |
145 | * translate ns coding of SPD timing values | |
146 | * into 10 ps unit values | |
147 | */ | |
bf9e3b38 | 148 | static inline unsigned short NSto10PS (unsigned char spd_byte) |
c609719b | 149 | { |
bf9e3b38 | 150 | return (spd_byte * 100); |
c609719b WD |
151 | } |
152 | ||
153 | #ifdef CONFIG_ZUMA_V2 | |
bf9e3b38 | 154 | static int check_dimm (uchar slot, sdram_info_t * info) |
c609719b | 155 | { |
8bde7f77 | 156 | /* assume 2 dimms, 2 banks each 256M - we dont have an |
c609719b WD |
157 | * dimm i2c so rely on the detection routines later */ |
158 | ||
bf9e3b38 | 159 | memset (info, 0, sizeof (*info)); |
c609719b WD |
160 | |
161 | info->slot = slot; | |
162 | info->banks = 2; /* Detect later */ | |
bf9e3b38 | 163 | info->registered = 0; |
c609719b WD |
164 | info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit |
165 | but doesn't matter, both do same | |
166 | thing in setup_sdram() */ | |
bf9e3b38 WD |
167 | info->tpar = 3; |
168 | info->tras_clocks = 5; | |
169 | info->burst_len = 4; | |
c609719b WD |
170 | #ifdef CONFIG_ECC |
171 | info->ecc = 0; /* Detect later */ | |
172 | #endif /* CONFIG_ECC */ | |
173 | return 0; | |
174 | } | |
175 | ||
12f34241 WD |
176 | #elif defined(CONFIG_P3G4) |
177 | ||
bf9e3b38 | 178 | static int check_dimm (uchar slot, sdram_info_t * info) |
12f34241 | 179 | { |
bf9e3b38 | 180 | memset (info, 0, sizeof (*info)); |
12f34241 WD |
181 | |
182 | if (slot) | |
183 | return 0; | |
184 | ||
185 | info->slot = slot; | |
186 | info->banks = 1; | |
187 | info->registered = 0; | |
188 | info->drb_size = 4; | |
189 | info->tpar = 3; | |
190 | info->tras_clocks = 6; | |
191 | info->burst_len = 4; | |
192 | #ifdef CONFIG_ECC | |
193 | info->ecc = 2; | |
194 | #endif | |
195 | return 0; | |
196 | } | |
197 | ||
bf9e3b38 | 198 | #else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */ |
c609719b WD |
199 | |
200 | /* This code reads the SPD chip on the sdram and populates | |
201 | * the array which is passed in with the relevant information */ | |
bf9e3b38 | 202 | static int check_dimm (uchar slot, sdram_info_t * info) |
c609719b | 203 | { |
c609719b WD |
204 | uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; |
205 | int ret; | |
206 | uchar rows, cols, sdram_banks, supp_cal, width, cal_val; | |
207 | ulong tmemclk; | |
208 | uchar trp_clocks, trcd_clocks; | |
209 | uchar data[128]; | |
210 | ||
211 | get_clocks (); | |
212 | ||
bf9e3b38 | 213 | tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ |
c609719b WD |
214 | |
215 | #ifdef CONFIG_EVB64260_750CX | |
216 | if (0 != slot) { | |
bf9e3b38 WD |
217 | printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); |
218 | printf (" called with slot=%d insetad!\n", slot); | |
c609719b WD |
219 | return 0; |
220 | } | |
221 | #endif | |
bf9e3b38 | 222 | DP (puts ("before i2c read\n")); |
c609719b | 223 | |
bf9e3b38 | 224 | ret = i2c_read (addr, 0, 128, data, 0); |
c609719b | 225 | |
bf9e3b38 | 226 | DP (puts ("after i2c read\n")); |
c609719b WD |
227 | |
228 | /* zero all the values */ | |
bf9e3b38 | 229 | memset (info, 0, sizeof (*info)); |
c609719b WD |
230 | |
231 | if (ret) { | |
bf9e3b38 | 232 | DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); |
c609719b WD |
233 | return 0; |
234 | } | |
235 | ||
236 | /* first, do some sanity checks */ | |
237 | if (data[2] != 0x4) { | |
bf9e3b38 | 238 | printf ("Not SDRAM in slot %d\n", slot); |
c609719b WD |
239 | return 0; |
240 | } | |
241 | ||
242 | /* get various information */ | |
243 | rows = data[3]; | |
244 | cols = data[4]; | |
245 | info->banks = data[5]; | |
246 | sdram_banks = data[17]; | |
247 | width = data[13] & 0x7f; | |
248 | ||
bf9e3b38 WD |
249 | DP (printf |
250 | ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); | |
c609719b WD |
251 | |
252 | /* check if the memory is registered */ | |
253 | if (data[21] & (BIT1 | BIT4)) | |
254 | info->registered = 1; | |
255 | ||
256 | #ifdef CONFIG_ECC | |
257 | /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ | |
258 | info->ecc = (data[11] & 2) >> 1; | |
259 | #endif | |
260 | ||
261 | /* bit 1 is CL2, bit 2 is CL3 */ | |
262 | supp_cal = (data[18] & 0x6) >> 1; | |
263 | ||
264 | /* compute the relevant clock values */ | |
bf9e3b38 WD |
265 | trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk; |
266 | trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk; | |
267 | info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk; | |
c609719b | 268 | |
bf9e3b38 WD |
269 | DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", |
270 | trp_clocks, trcd_clocks, info->tras_clocks)); | |
c609719b WD |
271 | |
272 | /* try a CAS latency of 3 first... */ | |
273 | cal_val = 0; | |
274 | if (supp_cal & 3) { | |
bf9e3b38 | 275 | if (NS10to10PS (data[9]) <= tmemclk) |
c609719b WD |
276 | cal_val = 3; |
277 | } | |
278 | ||
279 | /* then 2... */ | |
280 | if (supp_cal & 2) { | |
bf9e3b38 | 281 | if (NS10to10PS (data[23]) <= tmemclk) |
c609719b WD |
282 | cal_val = 2; |
283 | } | |
284 | ||
bf9e3b38 | 285 | DP (printf ("cal_val = %d\n", cal_val)); |
c609719b WD |
286 | |
287 | /* bummer, did't work... */ | |
288 | if (cal_val == 0) { | |
bf9e3b38 | 289 | DP (printf ("Couldn't find a good CAS latency\n")); |
c609719b WD |
290 | return 0; |
291 | } | |
292 | ||
293 | /* get the largest delay -- these values need to all be the same | |
294 | * see Res#6 */ | |
295 | info->tpar = cal_val; | |
296 | if (trp_clocks > info->tpar) | |
297 | info->tpar = trp_clocks; | |
298 | if (trcd_clocks > info->tpar) | |
299 | info->tpar = trcd_clocks; | |
300 | ||
bf9e3b38 | 301 | DP (printf ("tpar set to: %d\n", info->tpar)); |
c609719b | 302 | |
6d0f6bcf | 303 | #ifdef CONFIG_SYS_BROKEN_CL2 |
bf9e3b38 | 304 | if (info->tpar == 2) { |
c609719b | 305 | info->tpar = 3; |
bf9e3b38 | 306 | DP (printf ("tpar fixed-up to: %d\n", info->tpar)); |
c609719b WD |
307 | } |
308 | #endif | |
309 | /* compute the module DRB size */ | |
bf9e3b38 WD |
310 | info->drb_size = |
311 | (((1 << (rows + cols)) * sdram_banks) * width) / _16M; | |
c609719b | 312 | |
bf9e3b38 | 313 | DP (printf ("drb_size set to: %d\n", info->drb_size)); |
c609719b WD |
314 | |
315 | /* find the burst len */ | |
316 | info->burst_len = data[16] & 0xf; | |
317 | if ((info->burst_len & 8) == 8) { | |
318 | info->burst_len = 1; | |
319 | } else if ((info->burst_len & 4) == 4) { | |
320 | info->burst_len = 0; | |
321 | } else { | |
322 | return 0; | |
323 | } | |
324 | ||
325 | info->slot = slot; | |
326 | return 0; | |
327 | } | |
328 | #endif /* ! CONFIG_ZUMA_V2 */ | |
329 | ||
bf9e3b38 | 330 | static int setup_sdram_common (sdram_info_t info[2]) |
c609719b | 331 | { |
8bde7f77 | 332 | ulong tmp; |
bf9e3b38 WD |
333 | int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2; |
334 | ||
335 | if (!info[0].banks && !info[1].banks) | |
336 | return 0; | |
337 | ||
338 | if (info[0].banks) { | |
339 | if (info[0].tpar > tpar) | |
340 | tpar = info[0].tpar; | |
341 | if (info[0].tras_clocks > tras_clocks) | |
342 | tras_clocks = info[0].tras_clocks; | |
343 | if (!info[0].registered) | |
344 | registered = 0; | |
3f85ce27 | 345 | if (info[0].ecc != 2) |
bf9e3b38 | 346 | ecc = 0; |
c609719b WD |
347 | } |
348 | ||
bf9e3b38 WD |
349 | if (info[1].banks) { |
350 | if (info[1].tpar > tpar) | |
351 | tpar = info[1].tpar; | |
352 | if (info[1].tras_clocks > tras_clocks) | |
353 | tras_clocks = info[1].tras_clocks; | |
354 | if (!info[1].registered) | |
355 | registered = 0; | |
356 | if (info[1].ecc != 2) | |
357 | ecc = 0; | |
c609719b WD |
358 | } |
359 | ||
360 | /* SDRAM configuration */ | |
bf9e3b38 | 361 | tmp = GTREGREAD (SDRAM_CONFIGURATION); |
c609719b WD |
362 | |
363 | /* Turn on physical interleave if both DIMMs | |
364 | * have even numbers of banks. */ | |
bf9e3b38 WD |
365 | if ((info[0].banks == 0 || info[0].banks == 2) && |
366 | (info[1].banks == 0 || info[1].banks == 2)) { | |
367 | /* physical interleave on */ | |
368 | tmp &= ~(1 << 15); | |
c609719b | 369 | } else { |
bf9e3b38 WD |
370 | /* physical interleave off */ |
371 | tmp |= (1 << 15); | |
c609719b WD |
372 | } |
373 | ||
374 | tmp |= (registered << 17); | |
375 | ||
376 | /* Use buffer 1 to return read data to the CPU | |
377 | * See Res #12 */ | |
378 | tmp |= (1 << 26); | |
379 | ||
bf9e3b38 WD |
380 | GT_REG_WRITE (SDRAM_CONFIGURATION, tmp); |
381 | DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION))); | |
c609719b WD |
382 | |
383 | /* SDRAM timing */ | |
384 | tmp = (((tpar == 3) ? 2 : 1) | | |
385 | (((tpar == 3) ? 2 : 1) << 2) | | |
bf9e3b38 | 386 | (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8)); |
c609719b WD |
387 | |
388 | #ifdef CONFIG_ECC | |
389 | /* Setup ECC */ | |
bf9e3b38 WD |
390 | if (ecc == 2) |
391 | tmp |= 1 << 13; | |
c609719b WD |
392 | #endif /* CONFIG_ECC */ |
393 | ||
bf9e3b38 WD |
394 | GT_REG_WRITE (SDRAM_TIMING, tmp); |
395 | DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n", | |
396 | GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks)); | |
c609719b WD |
397 | |
398 | /* SDRAM address decode register */ | |
399 | /* program this with the default value */ | |
bf9e3b38 WD |
400 | GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2); |
401 | DP (printf ("SDRAM decode: %08x\n", | |
402 | GTREGREAD (SDRAM_ADDRESS_DECODE))); | |
c609719b WD |
403 | |
404 | return 0; | |
405 | } | |
406 | ||
407 | /* sets up the GT properly with information passed in */ | |
bf9e3b38 | 408 | static int setup_sdram (sdram_info_t * info) |
c609719b WD |
409 | { |
410 | ulong tmp, check; | |
411 | ulong *addr = 0; | |
412 | int i; | |
413 | ||
414 | /* sanity checking */ | |
bf9e3b38 WD |
415 | if (!info->banks) |
416 | return 0; | |
c609719b WD |
417 | |
418 | /* ---------------------------- */ | |
419 | /* Program the GT with the discovered data */ | |
420 | ||
421 | /* bank parameters */ | |
bf9e3b38 | 422 | tmp = (0xf << 16); /* leave all virt bank pages open */ |
c609719b | 423 | |
bf9e3b38 | 424 | DP (printf ("drb_size: %d\n", info->drb_size)); |
c609719b WD |
425 | switch (info->drb_size) { |
426 | case 1: | |
427 | tmp |= (1 << 14); | |
428 | break; | |
429 | case 4: | |
430 | case 8: | |
431 | tmp |= (2 << 14); | |
432 | break; | |
433 | case 16: | |
434 | case 32: | |
435 | tmp |= (3 << 14); | |
436 | break; | |
437 | default: | |
bf9e3b38 | 438 | printf ("Error in dram size calculation\n"); |
c609719b WD |
439 | return 1; |
440 | } | |
441 | ||
442 | /* SDRAM bank parameters */ | |
443 | /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ | |
bf9e3b38 WD |
444 | GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); |
445 | GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); | |
446 | DP (printf | |
447 | ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, | |
448 | info->slot * 2, (info->slot * 2) + 1, tmp)); | |
c609719b WD |
449 | |
450 | /* set the SDRAM configuration for each bank */ | |
451 | for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { | |
bf9e3b38 | 452 | DP (printf ("*** Running a MRS cycle for bank %d ***\n", i)); |
c609719b WD |
453 | |
454 | /* map the bank */ | |
bf9e3b38 | 455 | memory_map_bank (i, 0, GB / 4); |
c609719b WD |
456 | |
457 | /* set SDRAM mode */ | |
bf9e3b38 WD |
458 | GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3); |
459 | check = GTREGREAD (SDRAM_OPERATION_MODE); | |
c609719b WD |
460 | |
461 | /* dummy write */ | |
462 | *addr = 0; | |
463 | ||
464 | /* wait for the command to complete */ | |
bf9e3b38 | 465 | while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0); |
c609719b WD |
466 | |
467 | /* switch back to normal operation mode */ | |
bf9e3b38 WD |
468 | GT_REG_WRITE (SDRAM_OPERATION_MODE, 0); |
469 | check = GTREGREAD (SDRAM_OPERATION_MODE); | |
c609719b WD |
470 | |
471 | /* unmap the bank */ | |
bf9e3b38 WD |
472 | memory_map_bank (i, 0, 0); |
473 | DP (printf ("*** MRS cycle for bank %d done ***\n", i)); | |
c609719b WD |
474 | } |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | /* | |
480 | * Check memory range for valid RAM. A simple memory test determines | |
481 | * the actually available RAM size between addresses `base' and | |
482 | * `base + maxsize'. Some (not all) hardware errors are detected: | |
483 | * - short between address lines | |
484 | * - short between data lines | |
485 | */ | |
bf9e3b38 | 486 | static long int dram_size (long int *base, long int maxsize) |
c609719b | 487 | { |
bf9e3b38 WD |
488 | volatile long int *addr, *b = base; |
489 | long int cnt, val, save1, save2; | |
c609719b WD |
490 | |
491 | #define STARTVAL (1<<20) /* start test at 1M */ | |
bf9e3b38 WD |
492 | for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); |
493 | cnt <<= 1) { | |
494 | addr = base + cnt; /* pointer arith! */ | |
495 | ||
496 | save1 = *addr; /* save contents of addr */ | |
497 | save2 = *b; /* save contents of base */ | |
498 | ||
499 | *addr = cnt; /* write cnt to addr */ | |
500 | *b = 0; /* put null at base */ | |
501 | ||
502 | /* check at base address */ | |
503 | if ((*b) != 0) { | |
504 | *addr = save1; /* restore *addr */ | |
505 | *b = save2; /* restore *b */ | |
506 | return (0); | |
507 | } | |
508 | val = *addr; /* read *addr */ | |
509 | ||
510 | *addr = save1; | |
511 | *b = save2; | |
512 | ||
513 | if (val != cnt) { | |
514 | /* fix boundary condition.. STARTVAL means zero */ | |
515 | if (cnt == STARTVAL / sizeof (long)) | |
516 | cnt = 0; | |
517 | return (cnt * sizeof (long)); | |
518 | } | |
519 | } | |
520 | return maxsize; | |
c609719b WD |
521 | } |
522 | ||
523 | /* ------------------------------------------------------------------------- */ | |
524 | ||
525 | /* U-Boot interface function to SDRAM init - this is where all the | |
526 | * controlling logic happens */ | |
9973e3c6 | 527 | phys_size_t initdram (int board_type) |
c609719b | 528 | { |
bf9e3b38 | 529 | ulong checkbank[4] = {[0 ... 3] = 0 }; |
c609719b | 530 | int bank_no; |
8bde7f77 | 531 | ulong total; |
c609719b WD |
532 | int nhr; |
533 | sdram_info_t dimm_info[2]; | |
534 | ||
535 | ||
536 | /* first, use the SPD to get info about the SDRAM */ | |
537 | ||
538 | /* check the NHR bit and skip mem init if it's already done */ | |
bf9e3b38 | 539 | nhr = get_hid0 () & (1 << 16); |
c609719b WD |
540 | |
541 | if (nhr) { | |
bf9e3b38 | 542 | printf ("Skipping SDRAM setup due to NHR bit being set\n"); |
c609719b WD |
543 | } else { |
544 | /* DIMM0 */ | |
bf9e3b38 | 545 | check_dimm (0, &dimm_info[0]); |
c609719b WD |
546 | |
547 | /* DIMM1 */ | |
bf9e3b38 WD |
548 | #ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ |
549 | check_dimm (1, &dimm_info[1]); | |
550 | #else /* CONFIG_EVB64260_750CX */ | |
551 | memset (&dimm_info[1], 0, sizeof (sdram_info_t)); | |
c609719b WD |
552 | #endif |
553 | ||
554 | /* unmap all banks */ | |
bf9e3b38 WD |
555 | memory_map_bank (0, 0, 0); |
556 | memory_map_bank (1, 0, 0); | |
557 | memory_map_bank (2, 0, 0); | |
558 | memory_map_bank (3, 0, 0); | |
c609719b WD |
559 | |
560 | /* Now, program the GT with the correct values */ | |
bf9e3b38 WD |
561 | if (setup_sdram_common (dimm_info)) { |
562 | printf ("Setup common failed.\n"); | |
c609719b WD |
563 | } |
564 | ||
bf9e3b38 WD |
565 | if (setup_sdram (&dimm_info[0])) { |
566 | printf ("Setup for DIMM1 failed.\n"); | |
c609719b WD |
567 | } |
568 | ||
bf9e3b38 WD |
569 | if (setup_sdram (&dimm_info[1])) { |
570 | printf ("Setup for DIMM2 failed.\n"); | |
c609719b WD |
571 | } |
572 | ||
573 | /* set the NHR bit */ | |
bf9e3b38 | 574 | set_hid0 (get_hid0 () | (1 << 16)); |
c609719b WD |
575 | } |
576 | /* next, size the SDRAM banks */ | |
577 | ||
578 | total = 0; | |
bf9e3b38 WD |
579 | if (dimm_info[0].banks > 0) |
580 | checkbank[0] = 1; | |
581 | if (dimm_info[0].banks > 1) | |
582 | checkbank[1] = 1; | |
c609719b | 583 | if (dimm_info[0].banks > 2) |
bf9e3b38 | 584 | printf ("Error, SPD claims DIMM1 has >2 banks\n"); |
c609719b | 585 | |
bf9e3b38 WD |
586 | if (dimm_info[1].banks > 0) |
587 | checkbank[2] = 1; | |
588 | if (dimm_info[1].banks > 1) | |
589 | checkbank[3] = 1; | |
c609719b | 590 | if (dimm_info[1].banks > 2) |
bf9e3b38 | 591 | printf ("Error, SPD claims DIMM2 has >2 banks\n"); |
c609719b WD |
592 | |
593 | /* Generic dram sizer: works even if we don't have i2c DIMMs, | |
594 | * as long as the timing settings are more or less correct */ | |
595 | ||
596 | /* | |
597 | * pass 1: size all the banks, using first bat (0-256M) | |
bf9e3b38 WD |
598 | * limitation: we only support 256M per bank due to |
599 | * us only having 1 BAT for all DRAM | |
c609719b | 600 | */ |
6d0f6bcf | 601 | for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { |
c609719b | 602 | /* skip over banks that are not populated */ |
bf9e3b38 | 603 | if (!checkbank[bank_no]) |
c609719b WD |
604 | continue; |
605 | ||
bf9e3b38 | 606 | DP (printf ("checking bank %d\n", bank_no)); |
c609719b | 607 | |
bf9e3b38 WD |
608 | memory_map_bank (bank_no, 0, GB / 4); |
609 | checkbank[bank_no] = dram_size (NULL, GB / 4); | |
610 | memory_map_bank (bank_no, 0, 0); | |
c609719b | 611 | |
bf9e3b38 | 612 | DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no])); |
c609719b WD |
613 | } |
614 | ||
615 | /* | |
616 | * pass 2: contiguously map each bank into physical address | |
bf9e3b38 | 617 | * space. |
c609719b | 618 | */ |
bf9e3b38 | 619 | dimm_info[0].banks = dimm_info[1].banks = 0; |
6d0f6bcf | 620 | for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { |
bf9e3b38 WD |
621 | if (!checkbank[bank_no]) |
622 | continue; | |
c609719b | 623 | |
bf9e3b38 WD |
624 | dimm_info[bank_no / 2].banks++; |
625 | dimm_info[bank_no / 2].size += checkbank[bank_no]; | |
c609719b | 626 | |
bf9e3b38 | 627 | memory_map_bank (bank_no, total, checkbank[bank_no]); |
c609719b | 628 | #ifdef MAP_PCI |
bf9e3b38 | 629 | memory_map_bank_pci (bank_no, total, checkbank[bank_no]); |
c609719b WD |
630 | #endif |
631 | total += checkbank[bank_no]; | |
632 | } | |
633 | ||
634 | #ifdef CONFIG_ECC | |
635 | #ifdef CONFIG_ZUMA_V2 | |
636 | /* | |
637 | * We always enable ECC when bank 2 and 3 are unpopulated | |
638 | * If we 2 or 3 are populated, we CAN'T support ECC. | |
639 | * (Zuma boards only support ECC in banks 0 and 1; assume that | |
640 | * in that configuration, ECC chips are mounted, even for stacked | |
641 | * chips) | |
642 | */ | |
bf9e3b38 WD |
643 | if (checkbank[2] == 0 && checkbank[3] == 0) { |
644 | dimm_info[0].ecc = 2; | |
645 | GT_REG_WRITE (SDRAM_TIMING, | |
646 | GTREGREAD (SDRAM_TIMING) | (1 << 13)); | |
c609719b WD |
647 | /* TODO: do we have to run MRS cycles again? */ |
648 | } | |
649 | #endif /* CONFIG_ZUMA_V2 */ | |
650 | ||
bf9e3b38 WD |
651 | if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) { |
652 | puts ("[ECC] "); | |
c609719b WD |
653 | } |
654 | #endif /* CONFIG_ECC */ | |
655 | ||
656 | #ifdef DEBUG | |
bf9e3b38 WD |
657 | dump_dimm_info (&dimm_info[0]); |
658 | dump_dimm_info (&dimm_info[1]); | |
c609719b WD |
659 | #endif |
660 | /* TODO: return at MOST 256M? */ | |
8bde7f77 | 661 | /* return total > GB/4 ? GB/4 : total; */ |
c609719b WD |
662 | return total; |
663 | } |