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rename CFG_ macros to CONFIG_SYS
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2d39b71f 1/*
180d3f74 2 * (C) Copyright 2000-2004
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
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5 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
6 * and Dan Malek
7 *
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
9 *
10 * This header file contains values common to all FADS family boards.
11 *
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12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31/****************************************************************************
180d3f74 32 * Flash Memory Map as used by U-Boot:
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33 *
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
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36 * | | 0xFE00_0100 Reset Vector
37 * + + 0xFE0?_????
38 * | U-Boot code |
39 * | |
40 * +-----------------------+ 0xFE04_0000 (sector border)
41 * | |
42 * | |
43 * | U-Boot environment |
44 * | | ^
45 * | | | U-Boot
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
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48 * | ... | v
49 *
50 *****************************************************************************/
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51
52#if 0
53#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
54#else
55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56#endif
57
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58#define CONFIG_ENV_OVERWRITE
59
60#define CONFIG_NFSBOOTCOMMAND \
180d3f74 61 "dhcp;" \
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62 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
63 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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64 "bootm"
65
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66#define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
69 "bootm fe080000"
70
71#undef CONFIG_BOOTARGS
72
180d3f74 73#undef CONFIG_WATCHDOG /* watchdog disabled */
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74
75#if !defined(CONFIG_MPC885ADS)
1114257c 76#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
78f9fef7 77#endif
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78
79/*
8ff0208d 80 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
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81 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
82 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
83 * got FEC so FEC is the default.
84 */
85#ifndef CONFIG_ADS
86#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
87#define CONFIG_FEC_ENET /* Use FEC ethernet */
88#else /* Old ADS has not got FEC option */
89#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
90#undef CONFIG_FEC_ENET /* No FEC ethernet */
91#endif /* !CONFIG_ADS */
92
93#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
94#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
95#endif
96
97#ifdef CONFIG_FEC_ENET
6d0f6bcf 98#define CONFIG_SYS_DISCOVER_PHY
0f3ba7e9 99#define CONFIG_MII_INIT 1
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100#endif
101
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102
103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_BOOTFILESIZE
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_GATEWAY
109#define CONFIG_BOOTP_HOSTNAME
110
111
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112#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
113/*
114 * Command line configuration.
115 */
116#include <config_cmd_default.h>
117
118#define CONFIG_CMD_ASKENV
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_ECHO
121#define CONFIG_CMD_IMMAP
122#define CONFIG_CMD_JFFS2
123#define CONFIG_CMD_MII
124#define CONFIG_CMD_PCMCIA
125#define CONFIG_CMD_PING
126
127#endif
180d3f74 128
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129
130/*
131 * Miscellaneous configurable options
132 */
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133#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
134#define CONFIG_SYS_HUSH_PARSER
135#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
136#define CONFIG_SYS_LONGHELP /* #undef to save memory */
c508a4ce 137#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 138#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
180d3f74 139#else
6d0f6bcf 140#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
180d3f74 141#endif
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142#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
143#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
144#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
180d3f74 145
6d0f6bcf 146#define CONFIG_SYS_LOAD_ADDR 0x00100000
180d3f74 147
6d0f6bcf 148#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
180d3f74 149
6d0f6bcf 150#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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151
152/*
153 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here.
156 */
8ff0208d 157
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158/*-----------------------------------------------------------------------
159 * Internal Memory Mapped Register
160 */
6d0f6bcf 161#define CONFIG_SYS_IMMR 0xFF000000
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162
163/*-----------------------------------------------------------------------
164 * Definitions for initial stack pointer and data area (in DPRAM)
165 */
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166#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
167#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
168#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
169#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
170#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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171
172/*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
6d0f6bcf 175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
180d3f74 176 */
6d0f6bcf 177#define CONFIG_SYS_SDRAM_BASE 0x00000000
1114257c 178#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
6d0f6bcf 179#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
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180/*
181 * 2048 SDRAM rows
182 * 1000 factor s -> ms
183 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
184 * 4 Number of refresh cycles per period
185 * 64 Refresh cycle in ms per number of rows
186 */
6d0f6bcf 187#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
180d3f74 188#elif defined(CONFIG_FADS) /* Old/new FADS */
6d0f6bcf 189#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
180d3f74 190#else /* Old ADS */
6d0f6bcf 191#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */
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192#endif
193
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194#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
195#if (CONFIG_SYS_SDRAM_SIZE)
196#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
180d3f74 197#else
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198#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
199#endif /* CONFIG_SYS_SDRAM_SIZE */
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200
201/*
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
205 */
6d0f6bcf 206#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
99edcfb2 207
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208#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
209#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
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210
211#ifdef CONFIG_BZIP2
6d0f6bcf 212#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
99edcfb2 213#else
6d0f6bcf 214#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
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215#endif /* CONFIG_BZIP2 */
216
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217/*-----------------------------------------------------------------------
218 * Flash organization
219 */
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220#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
221#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
180d3f74 222
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223#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
224#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
180d3f74 225
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226#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
227#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
180d3f74 228
5a1aceb0 229#define CONFIG_ENV_IS_IN_FLASH 1
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230#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
231#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE
232#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
6d0f6bcf 233#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
180d3f74 234
6d0f6bcf 235#define CONFIG_SYS_DIRECT_FLASH_TFTP
1114257c 236
c508a4ce 237#if defined(CONFIG_CMD_JFFS2)
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238
239/*
240 * JFFS2 partitions
241 *
242 */
243/* No command line, one static partition, whole device */
244#undef CONFIG_JFFS2_CMDLINE
245#define CONFIG_JFFS2_DEV "nor0"
246#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
247#define CONFIG_JFFS2_PART_OFFSET 0x00000000
248
249/* mtdparts command line support */
250/* Note: fake mtd_id used, no linux mtd map file */
251/*
252#define CONFIG_JFFS2_CMDLINE
253#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
254#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
255*/
256
6d0f6bcf 257#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
77a31854 258#endif
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259
260/*-----------------------------------------------------------------------
261 * Cache Configuration
262 */
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263#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
264#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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265
266/*-----------------------------------------------------------------------
267 * I2C configuration
268 */
c508a4ce 269#if defined(CONFIG_CMD_I2C)
180d3f74 270#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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271#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */
272#define CONFIG_SYS_I2C_SLAVE 0x7F
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273#endif
274
275/*-----------------------------------------------------------------------
276 * SYPCR - System Protection Control 11-9
277 * SYPCR can only be written once after reset!
278 *-----------------------------------------------------------------------
279 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
280 */
281#if defined(CONFIG_WATCHDOG)
6d0f6bcf 282#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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283 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
284#else
6d0f6bcf 285#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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286#endif
287
288/*-----------------------------------------------------------------------
289 * SIUMCR - SIU Module Configuration 11-6
290 *-----------------------------------------------------------------------
291 * PCMCIA config., multi-function pin tri-state
292 */
6d0f6bcf 293#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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294
295/*-----------------------------------------------------------------------
296 * TBSCR - Time Base Status and Control 11-26
297 *-----------------------------------------------------------------------
298 * Clear Reference Interrupt Status, Timebase freezing enabled
299 */
6d0f6bcf 300#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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301
302/*-----------------------------------------------------------------------
303 * PISCR - Periodic Interrupt Status and Control 11-31
304 *-----------------------------------------------------------------------
305 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
306 */
6d0f6bcf 307#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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308
309/*-----------------------------------------------------------------------
310 * SCCR - System Clock and reset Control Register 15-27
311 *-----------------------------------------------------------------------
312 * Set clock output, timebase and RTC source and divider,
313 * power management and some other internal clocks
314 */
315#define SCCR_MASK SCCR_EBDF11
6d0f6bcf 316#define CONFIG_SYS_SCCR SCCR_TBS
180d3f74 317
1114257c 318/*-----------------------------------------------------------------------
8ff0208d 319 * DER - Debug Enable Register
1114257c 320 *-----------------------------------------------------------------------
8ff0208d 321 * Set to zero to prevent the processor from entering debug mode
180d3f74 322 */
6d0f6bcf 323#define CONFIG_SYS_DER 0
180d3f74 324
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325/* Because of the way the 860 starts up and assigns CS0 the entire
326 * address space, we have to set the memory controller differently.
327 * Normally, you write the option register first, and then enable the
328 * chip select by writing the base register. For CS0, you must write
329 * the base register first, followed by the option register.
330 */
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331
332/*
333 * Init Memory Controller:
334 *
335 * BR0/OR0 (Flash)
336 * BR1/OR1 (BCSR)
337 */
338/* the other CS:s are determined by looking at parameters in BCSRx */
339
340#define BCSR_ADDR ((uint) 0xFF080000)
341
6d0f6bcf 342#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
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343
344/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
6d0f6bcf 345#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
180d3f74 346
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347#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */
348#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
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349
350/* BCSRx - Board Control and Status Registers */
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351#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
352#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
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353
354/*
355 * Internal Definitions
356 *
357 * Boot Flags
358 */
359#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
360#define BOOTFLAG_WARM 0x02 /* Software reboot */
361
362/* values according to the manual */
363
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364#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
365#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
366#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
367#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
368#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
369
370/*
371 * (F)ADS bitvalues by Helmut Buchsbaum
372 *
373 * See User's Manual for a proper
374 * description of the following structures
375 */
376
377#define BCSR0_ERB ((uint)0x80000000)
378#define BCSR0_IP ((uint)0x40000000)
379#define BCSR0_BDIS ((uint)0x10000000)
380#define BCSR0_BPS_MASK ((uint)0x0C000000)
381#define BCSR0_ISB_MASK ((uint)0x01800000)
382#define BCSR0_DBGC_MASK ((uint)0x00600000)
383#define BCSR0_DBPC_MASK ((uint)0x00180000)
384#define BCSR0_EBDF_MASK ((uint)0x00060000)
385
386#define BCSR1_FLASH_EN ((uint)0x80000000)
387#define BCSR1_DRAM_EN ((uint)0x40000000)
388#define BCSR1_ETHEN ((uint)0x20000000)
389#define BCSR1_IRDEN ((uint)0x10000000)
390#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
391#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
392#define BCSR1_BCSR_EN ((uint)0x02000000)
393#define BCSR1_RS232EN_1 ((uint)0x01000000)
394#define BCSR1_PCCEN ((uint)0x00800000)
395#define BCSR1_PCCVCC0 ((uint)0x00400000)
396#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
397#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
398#define BCSR1_RS232EN_2 ((uint)0x00040000)
399#define BCSR1_SDRAM_EN ((uint)0x00020000)
400#define BCSR1_PCCVCC1 ((uint)0x00010000)
401
402#define BCSR1_PCCVCCON BCSR1_PCCVCC0
403
404#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
99edcfb2 405#define BCSR2_FLASH_PD_SHIFT 28
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406#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
407#define BCSR2_DRAM_PD_SHIFT 23
408#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
409#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
410
411#define BCSR3_DBID_MASK ((ushort)0x3800)
412#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
413#define BCSR3_BREVNR0 ((ushort)0x0080)
414#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
415#define BCSR3_BREVN1 ((ushort)0x0008)
416#define BCSR3_BREVN2_MASK ((ushort)0x0003)
417
418#define BCSR4_ETHLOOP ((uint)0x80000000)
419#define BCSR4_TFPLDL ((uint)0x40000000)
420#define BCSR4_TPSQEL ((uint)0x20000000)
421#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
8ff0208d 422#if defined(CONFIG_MPC823)
180d3f74 423#define BCSR4_USB_EN ((uint)0x08000000)
180d3f74 424#define BCSR4_USB_SPEED ((uint)0x04000000)
180d3f74 425#define BCSR4_VCCO ((uint)0x02000000)
180d3f74 426#define BCSR4_VIDEO_ON ((uint)0x00800000)
180d3f74 427#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
180d3f74 428#define BCSR4_VIDEO_RST ((uint)0x00200000)
180d3f74 429#define BCSR4_MODEM_EN ((uint)0x00100000)
180d3f74 430#define BCSR4_DATA_VOICE ((uint)0x00080000)
8ff0208d 431#elif defined(CONFIG_MPC850)
180d3f74 432#define BCSR4_DATA_VOICE ((uint)0x00080000)
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433#elif defined(CONFIG_MPC860SAR)
434#define BCSR4_UTOPIA_EN ((uint)0x08000000)
435#else /* MPC860T and other chips with FEC */
436#define BCSR4_FETH_EN ((uint)0x08000000)
437#define BCSR4_FETHCFG0 ((uint)0x04000000)
438#define BCSR4_FETHFDE ((uint)0x02000000)
439#define BCSR4_FETHCFG1 ((uint)0x00400000)
440#define BCSR4_FETHRST ((uint)0x00200000)
441#endif
180d3f74 442
8ff0208d 443/* BSCR5 exists on MPC86xADS and MPC885ADS only */
1114257c 444
6d0f6bcf 445#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
1114257c 446
6d0f6bcf 447#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300)
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448
449#define BCSR5_MII2_EN 0x40
450#define BCSR5_MII2_RST 0x20
451#define BCSR5_T1_RST 0x10
452#define BCSR5_ATM155_RST 0x08
453#define BCSR5_ATM25_RST 0x04
454#define BCSR5_MII1_EN 0x02
455#define BCSR5_MII1_RST 0x01
456
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457/* We don't use the 8259.
458*/
459#define NR_8259_INTS 0
460
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461/*-----------------------------------------------------------------------
462 * PCMCIA stuff
463 *-----------------------------------------------------------------------
464 */
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465#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
466#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
467#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
468#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
469#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
470#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
471#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
472#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
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473
474/*-----------------------------------------------------------------------
475 * IDE/ATA stuff
476 *-----------------------------------------------------------------------
477 */
478#define CONFIG_MAC_PARTITION 1
479#define CONFIG_DOS_PARTITION 1
480#define CONFIG_ISO_PARTITION 1
481
482#undef CONFIG_ATAPI
77a31854 483#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
180d3f74 484#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
966083e9 485#endif
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486#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
487#undef CONFIG_IDE_LED /* LED for ide not supported */
488#undef CONFIG_IDE_RESET /* reset for ide not supported */
489
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490#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
491#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
180d3f74 492
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493#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
494#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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495
496/* Offset for data I/O */
6d0f6bcf 497#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
180d3f74 498/* Offset for normal register accesses */
6d0f6bcf 499#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
180d3f74 500/* Offset for alternate registers */
6d0f6bcf 501#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
180d3f74
WD
502
503#define CONFIG_DISK_SPINUP_TIME 1000000
8ff0208d 504/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */