[people/ms/u-boot.git] / board / freescale / common / pixis.c

/*
 * Copyright 2006 Freescale Semiconductor
 * Jeff Brown
 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>

#include "pixis.h"


static ulong strfractoint(uchar *strptr);


/*
 * Simple board reset.
 */
void pixis_reset(void)
{
    out8(PIXIS_BASE + PIXIS_RST, 0);
}


/*
 * Per table 27, page 58 of MPC8641HPCN spec.
 */
int set_px_sysclk(ulong sysclk)
{
	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;

	switch (sysclk) {
	case 33:
		sysclk_s = 0x04;
		sysclk_r = 0x04;
		sysclk_v = 0x07;
		sysclk_aux = 0x00;
		break;
	case 40:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x20;
		sysclk_aux = 0x01;
		break;
	case 50:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x2A;
		sysclk_aux = 0x02;
		break;
	case 66:
		sysclk_s = 0x01;
		sysclk_r = 0x04;
		sysclk_v = 0x04;
		sysclk_aux = 0x03;
		break;
	case 83:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x04;
		break;
	case 100:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x5C;
		sysclk_aux = 0x05;
		break;
	case 134:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x3B;
		sysclk_aux = 0x06;
		break;
	case 166:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x07;
		break;
	default:
		printf("Unsupported SYSCLK frequency.\n");
		return 0;
	}

	vclkh = (sysclk_s << 5) | sysclk_r;
	vclkl = sysclk_v;

	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);

	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);

	return 1;
}


int set_px_mpxpll(ulong mpxpll)
{
	u8 tmp;
	u8 val;

	switch (mpxpll) {
	case 2:
	case 4:
	case 6:
	case 8:
	case 10:
	case 12:
	case 14:
	case 16:
		val = (u8) mpxpll;
		break;
	default:
		printf("Unsupported MPXPLL ratio.\n");
		return 0;
	}

	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
	tmp = (tmp & 0xF0) | (val & 0x0F);
	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);

	return 1;
}


int set_px_corepll(ulong corepll)
{
	u8 tmp;
	u8 val;

	switch ((int)corepll) {
	case 20:
		val = 0x08;
		break;
	case 25:
		val = 0x0C;
		break;
	case 30:
		val = 0x10;
		break;
	case 35:
		val = 0x1C;
		break;
	case 40:
		val = 0x14;
		break;
	case 45:
		val = 0x0E;
		break;
	default:
		printf("Unsupported COREPLL ratio.\n");
		return 0;
	}

	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
	tmp = (tmp & 0xE0) | (val & 0x1F);
	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);

	return 1;
}


void read_from_px_regs(int set)
{
	u8 mask = 0x1C;
	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);

	if (set)
		tmp = tmp | mask;
	else
		tmp = tmp & ~mask;
	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
}


void read_from_px_regs_altbank(int set)
{
	u8 mask = 0x04;
	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);

	if (set)
		tmp = tmp | mask;
	else
		tmp = tmp & ~mask;
	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}

#ifndef CFG_PIXIS_VBOOT_MASK
#define CFG_PIXIS_VBOOT_MASK	0x40
#endif

void set_altbank(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
	tmp ^= CFG_PIXIS_VBOOT_MASK;

	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}


void set_px_go(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp & 0x1E;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp | 0x01;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
}


void set_px_go_with_watchdog(void)
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp & 0x1E;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp | 0x09;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
}


int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
			       int flag, int argc, char *argv[])
{
	u8 tmp;

	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp = tmp & 0x1E;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	/* setting VCTL[WDEN] to 0 to disable watch dog */
	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	tmp &= ~0x08;
	out8(PIXIS_BASE + PIXIS_VCTL, tmp);

	return 0;
}

U_BOOT_CMD(
	   diswd, 1, 0, pixis_disable_watchdog_cmd,
	   "diswd	- Disable watchdog timer \n",
	   NULL);

/*
 * This function takes the non-integral cpu:mpx pll ratio
 * and converts it to an integer that can be used to assign
 * FPGA register values.
 * input: strptr i.e. argv[2]
 */

static ulong strfractoint(uchar *strptr)
{
	int i, j, retval;
	int mulconst;
	int intarr_len = 0, decarr_len = 0, no_dec = 0;
	ulong intval = 0, decval = 0;
	uchar intarr[3], decarr[3];

	/* Assign the integer part to intarr[]
	 * If there is no decimal point i.e.
	 * if the ratio is an integral value
	 * simply create the intarr.
	 */
	i = 0;
	while (strptr[i] != 46) {
		if (strptr[i] == 0) {
			no_dec = 1;
			break;
		}
		intarr[i] = strptr[i];
		i++;
	}

	/* Assign length of integer part to intarr_len. */
	intarr_len = i;
	intarr[i] = '\0';

	if (no_dec) {
		/* Currently needed only for single digit corepll ratios */
		mulconst = 10;
		decval = 0;
	} else {
		j = 0;
		i++;		/* Skipping the decimal point */
		while ((strptr[i] > 47) && (strptr[i] < 58)) {
			decarr[j] = strptr[i];
			i++;
			j++;
		}

		decarr_len = j;
		decarr[j] = '\0';

		mulconst = 1;
		for (i = 0; i < decarr_len; i++)
			mulconst *= 10;
		decval = simple_strtoul((char *)decarr, NULL, 10);
	}

	intval = simple_strtoul((char *)intarr, NULL, 10);
	intval = intval * mulconst;

	retval = intval + decval;

	return retval;
}


int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong val;
	ulong corepll;

	/*
	 * No args is a simple reset request.
	 */
	if (argc <= 1) {
		pixis_reset();
		/* not reached */
	}

	if (strcmp(argv[1], "cf") == 0) {

		/*
		 * Reset with frequency changed:
		 *    cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
		 */
		if (argc < 5) {
			puts(cmdtp->usage);
			return 1;
		}

		read_from_px_regs(0);

		val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));

		corepll = strfractoint((uchar *)argv[3]);
		val = val + set_px_corepll(corepll);
		val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
		if (val == 3) {
			puts("Setting registers VCFGEN0 and VCTL\n");
			read_from_px_regs(1);
			puts("Resetting board with values from ");
			puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
			set_px_go();
		} else {
			puts(cmdtp->usage);
			return 1;
		}

		while (1) ;	/* Not reached */

	} else if (strcmp(argv[1], "altbank") == 0) {

		/*
		 * Reset using alternate flash bank:
		 */
		if (argv[2] == 0) {
			/*
			 * Reset from alternate bank without changing
			 * frequency and without watchdog timer enabled.
			 *	altbank
			 */
			read_from_px_regs(0);
			read_from_px_regs_altbank(0);
			if (argc > 2) {
				puts(cmdtp->usage);
				return 1;
			}
			puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
			set_altbank();
			read_from_px_regs_altbank(1);
			puts("Resetting board to boot from the other bank.\n");
			set_px_go();

		} else if (strcmp(argv[2], "cf") == 0) {
			/*
			 * Reset with frequency changed
			 *    altbank cf <SYSCLK freq> <COREPLL ratio>
			 *				<MPXPLL ratio>
			 */
			read_from_px_regs(0);
			read_from_px_regs_altbank(0);
			val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
			corepll = strfractoint((uchar *)argv[4]);
			val = val + set_px_corepll(corepll);
			val = val + set_px_mpxpll(simple_strtoul(argv[5],
								 NULL, 10));
			if (val == 3) {
				puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
				set_altbank();
				read_from_px_regs(1);
				read_from_px_regs_altbank(1);
				puts("Enabling watchdog timer on the FPGA\n");
				puts("Resetting board with values from ");
				puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
				puts("to boot from the other bank.\n");
				set_px_go_with_watchdog();
			} else {
				puts(cmdtp->usage);
				return 1;
			}

			while (1) ;	/* Not reached */

		} else if (strcmp(argv[2], "wd") == 0) {
			/*
			 * Reset from alternate bank without changing
			 * frequencies but with watchdog timer enabled:
			 *    altbank wd
			 */
			read_from_px_regs(0);
			read_from_px_regs_altbank(0);
			puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
			set_altbank();
			read_from_px_regs_altbank(1);
			puts("Enabling watchdog timer on the FPGA\n");
			puts("Resetting board to boot from the other bank.\n");
			set_px_go_with_watchdog();
			while (1) ;	/* Not reached */

		} else {
			puts(cmdtp->usage);
			return 1;
		}

	} else {
		puts(cmdtp->usage);
		return 1;
	}

	return 0;
}


U_BOOT_CMD(
	pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
	"pixis_reset - Reset the board using the FPGA sequencer\n",
	"    pixis_reset\n"
	"    pixis_reset [altbank]\n"
	"    pixis_reset altbank wd\n"
	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	);
Commit	Line	Data
126aa70f JL	1	/*
	2	* Copyright 2006 Freescale Semiconductor
	3	* Jeff Brown
	4	* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
126aa70f	26	#include <command.h>
3d98b858	27	#include <watchdog.h>
314d5b6c	28	#include <asm/cache.h>
ad8f8687	29
126aa70f JL	30	#include "pixis.h"
	31
	32
3d98b858 HW	33	static ulong strfractoint(uchar *strptr);
	34
	35
	36	/*
	37	* Simple board reset.
	38	*/
	39	void pixis_reset(void)
	40	{
	41	out8(PIXIS_BASE + PIXIS_RST, 0);
	42	}
	43
	44
126aa70f JL	45	/*
	46	* Per table 27, page 58 of MPC8641HPCN spec.
	47	*/
	48	int set_px_sysclk(ulong sysclk)
	49	{
	50	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
	51
	52	switch (sysclk) {
	53	case 33:
	54	sysclk_s = 0x04;
	55	sysclk_r = 0x04;
	56	sysclk_v = 0x07;
	57	sysclk_aux = 0x00;
	58	break;
	59	case 40:
	60	sysclk_s = 0x01;
	61	sysclk_r = 0x1F;
	62	sysclk_v = 0x20;
	63	sysclk_aux = 0x01;
	64	break;
	65	case 50:
	66	sysclk_s = 0x01;
	67	sysclk_r = 0x1F;
	68	sysclk_v = 0x2A;
	69	sysclk_aux = 0x02;
	70	break;
	71	case 66:
	72	sysclk_s = 0x01;
	73	sysclk_r = 0x04;
	74	sysclk_v = 0x04;
	75	sysclk_aux = 0x03;
	76	break;
	77	case 83:
	78	sysclk_s = 0x01;
	79	sysclk_r = 0x1F;
	80	sysclk_v = 0x4B;
	81	sysclk_aux = 0x04;
	82	break;
	83	case 100:
	84	sysclk_s = 0x01;
	85	sysclk_r = 0x1F;
	86	sysclk_v = 0x5C;
	87	sysclk_aux = 0x05;
	88	break;
	89	case 134:
	90	sysclk_s = 0x06;
	91	sysclk_r = 0x1F;
	92	sysclk_v = 0x3B;
	93	sysclk_aux = 0x06;
	94	break;
	95	case 166:
	96	sysclk_s = 0x06;
	97	sysclk_r = 0x1F;
	98	sysclk_v = 0x4B;
	99	sysclk_aux = 0x07;
	100	break;
	101	default:
	102	printf("Unsupported SYSCLK frequency.\n");
	103	return 0;
	104	}
	105
80e955c7	106	vclkh = (sysclk_s << 5) \| sysclk_r;
126aa70f JL	107	vclkl = sysclk_v;
	108
	109	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
	110	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
	111
80e955c7	112	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
126aa70f JL	113
	114	return 1;
	115	}
	116
	117
	118	int set_px_mpxpll(ulong mpxpll)
	119	{
	120	u8 tmp;
	121	u8 val;
	122
	123	switch (mpxpll) {
	124	case 2:
	125	case 4:
	126	case 6:
	127	case 8:
	128	case 10:
	129	case 12:
	130	case 14:
	131	case 16:
80e955c7	132	val = (u8) mpxpll;
126aa70f JL	133	break;
	134	default:
	135	printf("Unsupported MPXPLL ratio.\n");
	136	return 0;
	137	}
	138
	139	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
	140	tmp = (tmp & 0xF0) \| (val & 0x0F);
	141	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
	142
	143	return 1;
	144	}
	145
	146
	147	int set_px_corepll(ulong corepll)
	148	{
	149	u8 tmp;
	150	u8 val;
	151
	152	switch ((int)corepll) {
	153	case 20:
	154	val = 0x08;
	155	break;
	156	case 25:
	157	val = 0x0C;
	158	break;
	159	case 30:
	160	val = 0x10;
	161	break;
	162	case 35:
	163	val = 0x1C;
	164	break;
	165	case 40:
	166	val = 0x14;
	167	break;
	168	case 45:
	169	val = 0x0E;
	170	break;
	171	default:
	172	printf("Unsupported COREPLL ratio.\n");
	173	return 0;
	174	}
	175
	176	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
	177	tmp = (tmp & 0xE0) \| (val & 0x1F);
	178	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
	179
	180	return 1;
	181	}
	182
	183
	184	void read_from_px_regs(int set)
	185	{
	186	u8 mask = 0x1C;
	187	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	188
	189	if (set)
	190	tmp = tmp \| mask;
	191	else
	192	tmp = tmp & ~mask;
	193	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
	194	}
	195
	196
197	void read_from_px_regs_altbank(int set)
198	{
199	u8 mask = 0x04;
200	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
201
202	if (set)
203	tmp = tmp \| mask;
204	else
205	tmp = tmp & ~mask;
206	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
207	}
208
db74b3c1 JJ	209	#ifndef CFG_PIXIS_VBOOT_MASK
	210	#define CFG_PIXIS_VBOOT_MASK 0x40
	211	#endif
126aa70f JL	212
	213	void set_altbank(void)
	214	{
	215	u8 tmp;
	216
	217	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
db74b3c1	218	tmp ^= CFG_PIXIS_VBOOT_MASK;
126aa70f JL	219
	220	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
	221	}
	222
	223
	224	void set_px_go(void)
	225	{
	226	u8 tmp;
	227
	228	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	229	tmp = tmp & 0x1E;
	230	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	231
	232	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	233	tmp = tmp \| 0x01;
	234	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	235	}
	236
	237
	238	void set_px_go_with_watchdog(void)
	239	{
	240	u8 tmp;
	241
	242	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	243	tmp = tmp & 0x1E;
	244	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	245
	246	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	247	tmp = tmp \| 0x09;
	248	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	249	}
	250
	251
3d98b858 HW	252	int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
3d98b858 HW	253	int flag, int argc, char *argv[])
126aa70f JL	254	{
	255	u8 tmp;
	256
	257	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	258	tmp = tmp & 0x1E;
	259	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	260
	261	/* setting VCTL[WDEN] to 0 to disable watch dog */
	262	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
80e955c7	263	tmp &= ~0x08;
126aa70f JL	264	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	265
	266	return 0;
	267	}
	268
126aa70f	269	U_BOOT_CMD(
3d98b858	270	diswd, 1, 0, pixis_disable_watchdog_cmd,
80e955c7 JL	271	"diswd - Disable watchdog timer \n",
80e955c7 JL	272	NULL);
126aa70f JL	273
	274	/*
	275	* This function takes the non-integral cpu:mpx pll ratio
	276	* and converts it to an integer that can be used to assign
	277	* FPGA register values.
	278	* input: strptr i.e. argv[2]
	279	*/
	280
3d98b858	281	static ulong strfractoint(uchar *strptr)
126aa70f JL	282	{
	283	int i, j, retval;
	284	int mulconst;
	285	int intarr_len = 0, decarr_len = 0, no_dec = 0;
	286	ulong intval = 0, decval = 0;
	287	uchar intarr[3], decarr[3];
	288
	289	/* Assign the integer part to intarr[]
	290	* If there is no decimal point i.e.
	291	* if the ratio is an integral value
	292	* simply create the intarr.
	293	*/
	294	i = 0;
	295	while (strptr[i] != 46) {
	296	if (strptr[i] == 0) {
	297	no_dec = 1;
	298	break;
	299	}
	300	intarr[i] = strptr[i];
	301	i++;
	302	}
	303
	304	/* Assign length of integer part to intarr_len. */
	305	intarr_len = i;
	306	intarr[i] = '\0';
	307
	308	if (no_dec) {
	309	/* Currently needed only for single digit corepll ratios */
80e955c7	310	mulconst = 10;
126aa70f JL	311	decval = 0;
	312	} else {
	313	j = 0;
80e955c7	314	i++; /* Skipping the decimal point */
126aa70f JL	315	while ((strptr[i] > 47) && (strptr[i] < 58)) {
	316	decarr[j] = strptr[i];
	317	i++;
	318	j++;
	319	}
	320
	321	decarr_len = j;
	322	decarr[j] = '\0';
	323
	324	mulconst = 1;
	325	for (i = 0; i < decarr_len; i++)
	326	mulconst *= 10;
cdd917a4	327	decval = simple_strtoul((char *)decarr, NULL, 10);
126aa70f JL	328	}
126aa70f JL	329
cdd917a4	330	intval = simple_strtoul((char *)intarr, NULL, 10);
126aa70f JL	331	intval = intval * mulconst;
	332
	333	retval = intval + decval;
	334
	335	return retval;
	336	}
3d98b858 HW	337
	338
	339	int
	340	pixis_reset_cmd(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	341	{
	342	ulong val;
	343	ulong corepll;
	344
	345	/*
	346	* No args is a simple reset request.
	347	*/
	348	if (argc <= 1) {
	349	pixis_reset();
	350	/* not reached */
	351	}
	352
	353	if (strcmp(argv[1], "cf") == 0) {
	354
	355	/*
	356	* Reset with frequency changed:
	357	* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
	358	*/
	359	if (argc < 5) {
	360	puts(cmdtp->usage);
	361	return 1;
	362	}
	363
	364	read_from_px_regs(0);
	365
	366	val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
	367
cdd917a4	368	corepll = strfractoint((uchar *)argv[3]);
3d98b858 HW	369	val = val + set_px_corepll(corepll);
	370	val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
	371	if (val == 3) {
	372	puts("Setting registers VCFGEN0 and VCTL\n");
	373	read_from_px_regs(1);
	374	puts("Resetting board with values from ");
	375	puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
	376	set_px_go();
	377	} else {
	378	puts(cmdtp->usage);
	379	return 1;
	380	}
	381
	382	while (1) ; /* Not reached */
	383
	384	} else if (strcmp(argv[1], "altbank") == 0) {
	385
	386	/*
	387	* Reset using alternate flash bank:
	388	*/
	389	if (argv[2] == 0) {
	390	/*
	391	* Reset from alternate bank without changing
	392	* frequency and without watchdog timer enabled.
	393	* altbank
	394	*/
	395	read_from_px_regs(0);
	396	read_from_px_regs_altbank(0);
	397	if (argc > 2) {
	398	puts(cmdtp->usage);
	399	return 1;
	400	}
	401	puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
	402	set_altbank();
	403	read_from_px_regs_altbank(1);
	404	puts("Resetting board to boot from the other bank.\n");
	405	set_px_go();
	406
	407	} else if (strcmp(argv[2], "cf") == 0) {
	408	/*
	409	* Reset with frequency changed
	410	* altbank cf <SYSCLK freq> <COREPLL ratio>
	411	* <MPXPLL ratio>
	412	*/
	413	read_from_px_regs(0);
	414	read_from_px_regs_altbank(0);
	415	val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
cdd917a4	416	corepll = strfractoint((uchar *)argv[4]);
3d98b858 HW	417	val = val + set_px_corepll(corepll);
	418	val = val + set_px_mpxpll(simple_strtoul(argv[5],
	419	NULL, 10));
	420	if (val == 3) {
	421	puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
	422	set_altbank();
	423	read_from_px_regs(1);
	424	read_from_px_regs_altbank(1);
	425	puts("Enabling watchdog timer on the FPGA\n");
	426	puts("Resetting board with values from ");
	427	puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
	428	puts("to boot from the other bank.\n");
	429	set_px_go_with_watchdog();
	430	} else {
	431	puts(cmdtp->usage);
	432	return 1;
	433	}
	434
	435	while (1) ; /* Not reached */
	436
	437	} else if (strcmp(argv[2], "wd") == 0) {
	438	/*
	439	* Reset from alternate bank without changing
	440	* frequencies but with watchdog timer enabled:
	441	* altbank wd
	442	*/
	443	read_from_px_regs(0);
	444	read_from_px_regs_altbank(0);
	445	puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
	446	set_altbank();
	447	read_from_px_regs_altbank(1);
	448	puts("Enabling watchdog timer on the FPGA\n");
	449	puts("Resetting board to boot from the other bank.\n");
	450	set_px_go_with_watchdog();
	451	while (1) ; /* Not reached */
	452
	453	} else {
	454	puts(cmdtp->usage);
	455	return 1;
	456	}
	457
	458	} else {
	459	puts(cmdtp->usage);
	460	return 1;
	461	}
	462
	463	return 0;
	464	}
	465
	466
	467	U_BOOT_CMD(
	468	pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
	469	"pixis_reset - Reset the board using the FPGA sequencer\n",
	470	" pixis_reset\n"
	471	" pixis_reset [altbank]\n"
	472	" pixis_reset altbank wd\n"
	473	" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	474	" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	475	);