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2cddfcbc | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
d239d9d9 | 2 | /* |
2cddfcbc | 3 | * Copyright 2018-2019, 2021 NXP |
d239d9d9 | 4 | * |
d239d9d9 PF |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
09140113 | 8 | #include <command.h> |
9a3b4ceb | 9 | #include <cpu_func.h> |
db41d65a | 10 | #include <hang.h> |
4d72caa5 | 11 | #include <image.h> |
691d719d | 12 | #include <init.h> |
f7ae49fc | 13 | #include <log.h> |
d239d9d9 | 14 | #include <spl.h> |
401d1c4f | 15 | #include <asm/global_data.h> |
d239d9d9 PF |
16 | #include <asm/io.h> |
17 | #include <asm/mach-imx/iomux-v3.h> | |
18 | #include <asm/arch/clock.h> | |
19 | #include <asm/arch/imx8mn_pins.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <asm/mach-imx/boot_mode.h> | |
22 | #include <asm/arch/ddr.h> | |
506df9dc | 23 | #include <asm/sections.h> |
d239d9d9 PF |
24 | |
25 | #include <dm/uclass.h> | |
26 | #include <dm/device.h> | |
27 | #include <dm/uclass-internal.h> | |
28 | #include <dm/device-internal.h> | |
4e805c19 PF |
29 | #include <power/pmic.h> |
30 | #include <power/pca9450.h> | |
31 | #include <asm/mach-imx/gpio.h> | |
32 | #include <asm/mach-imx/mxc_i2c.h> | |
33 | #include <fsl_esdhc_imx.h> | |
34 | #include <mmc.h> | |
d239d9d9 PF |
35 | |
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
38 | int spl_board_boot_device(enum boot_device boot_dev_spl) | |
39 | { | |
40 | return BOOT_DEVICE_BOOTROM; | |
41 | } | |
42 | ||
43 | void spl_dram_init(void) | |
44 | { | |
45 | ddr_init(&dram_timing); | |
46 | } | |
47 | ||
48 | void spl_board_init(void) | |
49 | { | |
50 | struct udevice *dev; | |
51 | int ret; | |
52 | ||
1f908b18 MV |
53 | arch_misc_init(); |
54 | ||
d239d9d9 PF |
55 | puts("Normal Boot\n"); |
56 | ||
57 | ret = uclass_get_device_by_name(UCLASS_CLK, | |
58 | "clock-controller@30380000", | |
59 | &dev); | |
60 | if (ret < 0) | |
61 | printf("Failed to find clock node. Check device tree\n"); | |
62 | } | |
63 | ||
4e805c19 PF |
64 | #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) |
65 | int power_init_board(void) | |
66 | { | |
67 | struct udevice *dev; | |
68 | int ret; | |
69 | ||
4e5114da | 70 | ret = pmic_get("pmic@25", &dev); |
4e805c19 PF |
71 | if (ret == -ENODEV) { |
72 | puts("No pca9450@25\n"); | |
73 | return 0; | |
74 | } | |
75 | if (ret != 0) | |
76 | return ret; | |
77 | ||
78 | /* BUCKxOUT_DVS0/1 control BUCK123 output */ | |
79 | pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); | |
80 | ||
98bcdf16 YL |
81 | #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE |
82 | /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ | |
83 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); | |
84 | #else | |
4e805c19 | 85 | /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ |
98bcdf16 YL |
86 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); |
87 | #endif | |
4e805c19 PF |
88 | /* Set DVS1 to 0.85v for suspend */ |
89 | /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ | |
4e805c19 PF |
90 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); |
91 | pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); | |
92 | ||
93 | /* set VDD_SNVS_0V8 from default 0.85V */ | |
94 | pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); | |
95 | ||
96 | /* enable LDO4 to 1.2v */ | |
97 | pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); | |
98 | ||
4e805c19 PF |
99 | return 0; |
100 | } | |
101 | #endif | |
102 | ||
d239d9d9 PF |
103 | #ifdef CONFIG_SPL_LOAD_FIT |
104 | int board_fit_config_name_match(const char *name) | |
105 | { | |
106 | /* Just empty function now - can't decide what to choose */ | |
107 | debug("%s: %s\n", __func__, name); | |
108 | ||
109 | return 0; | |
110 | } | |
111 | #endif | |
112 | ||
d239d9d9 PF |
113 | void board_init_f(ulong dummy) |
114 | { | |
115 | int ret; | |
116 | ||
117 | arch_cpu_init(); | |
118 | ||
119 | init_uart_clk(1); | |
120 | ||
d239d9d9 PF |
121 | timer_init(); |
122 | ||
d239d9d9 PF |
123 | /* Clear the BSS. */ |
124 | memset(__bss_start, 0, __bss_end - __bss_start); | |
125 | ||
126 | ret = spl_init(); | |
127 | if (ret) { | |
128 | debug("spl_init() failed: %d\n", ret); | |
129 | hang(); | |
130 | } | |
131 | ||
a497740f PF |
132 | preloader_console_init(); |
133 | ||
d239d9d9 PF |
134 | enable_tzc380(); |
135 | ||
136 | /* DDR initialization */ | |
137 | spl_dram_init(); | |
138 | ||
139 | board_init_r(NULL, 0); | |
140 | } |