[thirdparty/u-boot.git] / board / freescale / ls2080aqds / ls2080aqds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor
 */
#include <common.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <i2c.h>
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"

#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
#include "../common/vid.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a
#define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)

DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
	char buf[64];
	u8 sw;
	static const char *const freq[] = {"100", "125", "156.25",
					    "100 separate SSCG"};
	int clock;

	cpu_name(buf);
	printf("Board: %s-QDS, ", buf);

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);

	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x8)
		puts("PromJet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else if (sw == 0xf)
		puts("QSPI\n");
	else if (sw == 0x15)
		printf("IFCCard\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));

	/*
	 * Display the actual SERDES reference clocks as configured by the
	 * dip switches on the board.  Note that the SWx registers could
	 * technically be set to force the reference clocks to match the
	 * values that the SERDES expects (or vice versa).  For now, however,
	 * we just display both values and hope the user notices when they
	 * don't match.
	 */
	puts("SERDES1 Reference : ");
	sw = QIXIS_READ(brdcfg[2]);
	clock = (sw >> 6) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 4) & 3;
	printf("Clock2 = %sMHz", freq[clock]);

	puts("\nSERDES2 Reference : ");
	clock = (sw >> 2) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 0) & 3;
	printf("Clock2 = %sMHz\n", freq[clock]);

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}
	return 66666666;
}

int config_board_mux(int ctrl_type)
{
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);

	return 0;
}

int board_init(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;

	init_final_memctl_regs();

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = env_get("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);

	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
		QIXIS_WRITE(brdcfg[9],
			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
			     FSL_QIXIS_BRDCFG9_QSPI);
#endif

	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);

#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#if CONFIG_IS_ENABLED(DM_I2C)
	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
#else
	rtc_enable_32khz_output();
#endif
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif

#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
	pci_init();
#endif

	return 0;
}

int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C_EARLY_INIT)
	i2c_early_init_f();
#endif
	fsl_lsch3_early_init_f();
#ifdef CONFIG_FSL_QSPI
	/* input clk: 1/2 platform clk, output: input/20 */
	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
#endif
	return 0;
}

int misc_init_r(void)
{
	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/soc/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0 &&
	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}

void board_quiesce_devices(void)
{
	fsl_mc_ldpaa_exit(gd->bd);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	fdt_fixup_memory_banks(blob, base, size, 2);

	fdt_fsl_mc_fixup_iommu_map_entry(blob);

	fsl_fdt_fixup_dr_usb(blob, bd);

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
	fdt_fixup_board_enet(blob);
#endif

	fdt_fixup_icid(blob);

	return 0;
}
#endif

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7288c2c2 YS	2	/*
7288c2c2 YS	3	* Copyright 2015 Freescale Semiconductor
7288c2c2 YS	4	*/
7288c2c2 YS	5	#include <common.h>
7b51b576	6	#include <env.h>
691d719d	7	#include <init.h>
7288c2c2 YS	8	#include <malloc.h>
	9	#include <errno.h>
	10	#include <netdev.h>
	11	#include <fsl_ifc.h>
	12	#include <fsl_ddr.h>
401d1c4f	13	#include <asm/global_data.h>
7288c2c2 YS	14	#include <asm/io.h>
7288c2c2 YS	15	#include <fdt_support.h>
b08c8c48	16	#include <linux/libfdt.h>
7288c2c2	17	#include <fsl-mc/fsl_mc.h>
f3998fdc	18	#include <env_internal.h>
7288c2c2	19	#include <i2c.h>
7fb79e65	20	#include <rtc.h>
9f3183d2	21	#include <asm/arch/soc.h>
e71a980a	22	#include <hwconfig.h>
fcfdb6d5	23	#include <fsl_sec.h>
54ad7b5a	24	#include <asm/arch/ppa.h>
e33938ac	25	#include <asm/arch-fsl-layerscape/fsl_icid.h>
17c2a308	26	#include "../common/i2c_mux.h"
7288c2c2 YS	27
7288c2c2 YS	28	#include "../common/qixis.h"
44937214	29	#include "ls2080aqds_qixis.h"
35cc100b	30	#include "../common/vid.h"
7288c2c2	31
e71a980a HW	32	#define PIN_MUX_SEL_SDHC 0x00
e71a980a HW	33	#define PIN_MUX_SEL_DSPI 0x0a
916d9f09	34	#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
e71a980a HW	35
	36	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
	37
7288c2c2 YS	38	DECLARE_GLOBAL_DATA_PTR;
7288c2c2 YS	39
e71a980a HW	40	enum {
	41	MUX_TYPE_SDHC,
	42	MUX_TYPE_DSPI,
	43	};
	44
7288c2c2 YS	45	unsigned long long get_qixis_addr(void)
	46	{
	47	unsigned long long addr;
	48
	49	if (gd->flags & GD_FLG_RELOC)
	50	addr = QIXIS_BASE_PHYS;
	51	else
	52	addr = QIXIS_BASE_PHYS_EARLY;
	53
	54	/*
	55	* IFC address under 256MB is mapped to 0x30000000, any address above
	56	* is mapped to 0x5_10000000 up to 4GB.
	57	*/
	58	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	59
	60	return addr;
	61	}
	62
	63	int checkboard(void)
	64	{
	65	char buf[64];
	66	u8 sw;
	67	static const char *const freq[] = {"100", "125", "156.25",
	68	"100 separate SSCG"};
	69	int clock;
	70
ff1b8e3f PK	71	cpu_name(buf);
	72	printf("Board: %s-QDS, ", buf);
	73
7288c2c2	74	sw = QIXIS_READ(arch);
7288c2c2 YS	75	printf("Board Arch: V%d, ", sw >> 4);
	76	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	77
ff1b8e3f PK	78	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
ff1b8e3f PK	79
7288c2c2 YS	80	sw = QIXIS_READ(brdcfg[0]);
	81	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	82
	83	if (sw < 0x8)
	84	printf("vBank: %d\n", sw);
	85	else if (sw == 0x8)
	86	puts("PromJet\n");
	87	else if (sw == 0x9)
	88	puts("NAND\n");
a646f669 YY	89	else if (sw == 0xf)
a646f669 YY	90	puts("QSPI\n");
7288c2c2 YS	91	else if (sw == 0x15)
	92	printf("IFCCard\n");
	93	else
	94	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	95
	96	printf("FPGA: v%d (%s), build %d",
	97	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	98	(int)qixis_read_minor());
	99	/* the timestamp string contains "\n" at the end */
	100	printf(" on %s", qixis_read_time(buf));
	101
	102	/*
	103	* Display the actual SERDES reference clocks as configured by the
	104	* dip switches on the board. Note that the SWx registers could
	105	* technically be set to force the reference clocks to match the
	106	* values that the SERDES expects (or vice versa). For now, however,
	107	* we just display both values and hope the user notices when they
	108	* don't match.
	109	*/
	110	puts("SERDES1 Reference : ");
	111	sw = QIXIS_READ(brdcfg[2]);
	112	clock = (sw >> 6) & 3;
	113	printf("Clock1 = %sMHz ", freq[clock]);
	114	clock = (sw >> 4) & 3;
	115	printf("Clock2 = %sMHz", freq[clock]);
	116
	117	puts("\nSERDES2 Reference : ");
	118	clock = (sw >> 2) & 3;
	119	printf("Clock1 = %sMHz ", freq[clock]);
	120	clock = (sw >> 0) & 3;
	121	printf("Clock2 = %sMHz\n", freq[clock]);
	122
	123	return 0;
	124	}
	125
	126	unsigned long get_board_sys_clk(void)
	127	{
	128	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	129
	130	switch (sysclk_conf & 0x0F) {
	131	case QIXIS_SYSCLK_83:
	132	return 83333333;
	133	case QIXIS_SYSCLK_100:
	134	return 100000000;
	135	case QIXIS_SYSCLK_125:
	136	return 125000000;
	137	case QIXIS_SYSCLK_133:
	138	return 133333333;
	139	case QIXIS_SYSCLK_150:
	140	return 150000000;
	141	case QIXIS_SYSCLK_160:
	142	return 160000000;
	143	case QIXIS_SYSCLK_166:
	144	return 166666666;
	145	}
	146	return 66666666;
	147	}
	148
	149	unsigned long get_board_ddr_clk(void)
	150	{
	151	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	152
	153	switch ((ddrclk_conf & 0x30) >> 4) {
	154	case QIXIS_DDRCLK_100:
155	return 100000000;
156	case QIXIS_DDRCLK_125:
157	return 125000000;
158	case QIXIS_DDRCLK_133:
159	return 133333333;
160	}
161	return 66666666;
162	}
163
e71a980a HW	164	int config_board_mux(int ctrl_type)
	165	{
	166	u8 reg5;
	167
	168	reg5 = QIXIS_READ(brdcfg[5]);
	169
	170	switch (ctrl_type) {
	171	case MUX_TYPE_SDHC:
	172	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	173	break;
	174	case MUX_TYPE_DSPI:
	175	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	176	break;
	177	default:
	178	printf("Wrong mux interface type\n");
	179	return -1;
	180	}
	181
	182	QIXIS_WRITE(brdcfg[5], reg5);
	183
	184	return 0;
	185	}
	186
7288c2c2 YS	187	int board_init(void)
7288c2c2 YS	188	{
e71a980a HW	189	char *env_hwconfig;
	190	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	191	u32 val;
	192
7288c2c2 YS	193	init_final_memctl_regs();
7288c2c2 YS	194
e71a980a HW	195	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
e71a980a HW	196
00caae6d	197	env_hwconfig = env_get("hwconfig");
e71a980a HW	198
	199	if (hwconfig_f("dspi", env_hwconfig) &&
	200	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	201	config_board_mux(MUX_TYPE_DSPI);
	202	else
	203	config_board_mux(MUX_TYPE_SDHC);
	204
88718be3	205	#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
453418f2 YY	206	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
	207
	208	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
	209	QIXIS_WRITE(brdcfg[9],
	210	(QIXIS_READ(brdcfg[9]) & 0xf8) \|
	211	FSL_QIXIS_BRDCFG9_QSPI);
	212	#endif
	213
17c2a308	214	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
885ae051	215
db07c447	216	#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
2147a169	217	#if CONFIG_IS_ENABLED(DM_I2C)
885ae051 CH	218	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
885ae051 CH	219	#else
7fb79e65	220	rtc_enable_32khz_output();
db07c447	221	#endif
885ae051 CH	222	#endif
885ae051 CH	223
15e7c681 UA	224	#ifdef CONFIG_FSL_CAAM
	225	sec_init();
	226	#endif
54ad7b5a SK	227
	228	#ifdef CONFIG_FSL_LS_PPA
	229	ppa_init();
	230	#endif
	231
8cbef912 IC	232	#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
	233	pci_init();
	234	#endif
	235
7288c2c2 YS	236	return 0;
	237	}
	238
	239	int board_early_init_f(void)
	240	{
52c7e375	241	#if defined(CONFIG_SYS_I2C_EARLY_INIT)
8c77ef85 YY	242	i2c_early_init_f();
8c77ef85 YY	243	#endif
7288c2c2	244	fsl_lsch3_early_init_f();
916d9f09 YY	245	#ifdef CONFIG_FSL_QSPI
	246	/* input clk: 1/2 platform clk, output: input/20 */
	247	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
	248	#endif
7288c2c2 YS	249	return 0;
	250	}
	251
35cc100b PJ	252	int misc_init_r(void)
	253	{
	254	if (adjust_vdd(0))
	255	printf("Warning: Adjusting core voltage failed.\n");
	256
	257	return 0;
	258	}
	259
7288c2c2 YS	260	void detail_board_ddr_info(void)
	261	{
	262	puts("\nDDR ");
	263	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	264	print_ddr_info(0);
44937214	265	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a	266	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
7288c2c2 YS	267	puts("\nDP-DDR ");
	268	print_size(gd->bd->bi_dram[2].size, "");
	269	print_ddr_info(CONFIG_DP_DDR_CTRL);
	270	}
44937214	271	#endif
7288c2c2 YS	272	}
7288c2c2 YS	273
1f55a938	274	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
7288c2c2 YS	275	void fdt_fixup_board_enet(void *fdt)
	276	{
	277	int offset;
	278
e91f1dec	279	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
7288c2c2 YS	280
7288c2c2 YS	281	if (offset < 0)
e91f1dec	282	offset = fdt_path_offset(fdt, "/fsl-mc");
7288c2c2 YS	283
	284	if (offset < 0) {
	285	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	286	__func__, offset);
	287	return;
	288	}
	289
7e968049 MYK	290	if (get_mc_boot_status() == 0 &&
7e968049 MYK	291	(is_lazy_dpl_addr_valid() \|\| get_dpl_apply_status() == 0))
7288c2c2 YS	292	fdt_status_okay(fdt, offset);
	293	else
	294	fdt_status_fail(fdt, offset);
	295	}
b7b8410a AG	296
	297	void board_quiesce_devices(void)
	298	{
	299	fsl_mc_ldpaa_exit(gd->bd);
	300	}
7288c2c2 YS	301	#endif
	302
	303	#ifdef CONFIG_OF_BOARD_SETUP
b75d8dc5	304	int ft_board_setup(void blob, struct bd_info bd)
7288c2c2	305	{
a2dc818f BS	306	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	307	u64 size[CONFIG_NR_DRAM_BANKS];
7288c2c2 YS	308
	309	ft_cpu_setup(blob, bd);
	310
a2dc818f BS	311	/* fixup DT for the two GPP DDR banks */
	312	base[0] = gd->bd->bi_dram[0].start;
	313	size[0] = gd->bd->bi_dram[0].size;
	314	base[1] = gd->bd->bi_dram[1].start;
	315	size[1] = gd->bd->bi_dram[1].size;
	316
36cc0de0 YS	317	#ifdef CONFIG_RESV_RAM
	318	/* reduce size if reserved memory is within this bank */
	319	if (gd->arch.resv_ram >= base[0] &&
	320	gd->arch.resv_ram < base[0] + size[0])
	321	size[0] = gd->arch.resv_ram - base[0];
	322	else if (gd->arch.resv_ram >= base[1] &&
	323	gd->arch.resv_ram < base[1] + size[1])
	324	size[1] = gd->arch.resv_ram - base[1];
	325	#endif
	326
a2dc818f	327	fdt_fixup_memory_banks(blob, base, size, 2);
7288c2c2	328
a78df40c NG	329	fdt_fsl_mc_fixup_iommu_map_entry(blob);
a78df40c NG	330
a5c289b9	331	fsl_fdt_fixup_dr_usb(blob, bd);
ef53b8c4	332
1f55a938	333	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
7288c2c2	334	fdt_fixup_board_enet(blob);
7288c2c2 YS	335	#endif
7288c2c2 YS	336
e33938ac LT	337	fdt_fixup_icid(blob);
e33938ac LT	338
7288c2c2 YS	339	return 0;
	340	}
	341	#endif
	342
	343	void qixis_dump_switch(void)
	344	{
	345	int i, nr_of_cfgsw;
	346
	347	QIXIS_WRITE(cms[0], 0x00);
	348	nr_of_cfgsw = QIXIS_READ(cms[1]);
	349
	350	puts("DIP switch settings dump:\n");
	351	for (i = 1; i <= nr_of_cfgsw; i++) {
	352	QIXIS_WRITE(cms[0], i);
	353	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	354	}
	355	}