[thirdparty/u-boot.git] / board / freescale / ls2080aqds / ls2080aqds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor
 * Copyright 2021 NXP
 */
#include <common.h>
#include <clock_legacy.h>
#include <display_options.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <i2c.h>
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"

#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
#include "../common/vid.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a
#define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)

DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
	char buf[64];
	u8 sw;
	static const char *const freq[] = {"100", "125", "156.25",
					    "100 separate SSCG"};
	int clock;

	cpu_name(buf);
	printf("Board: %s-QDS, ", buf);

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);

	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x8)
		puts("PromJet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else if (sw == 0xf)
		puts("QSPI\n");
	else if (sw == 0x15)
		printf("IFCCard\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));

	/*
	 * Display the actual SERDES reference clocks as configured by the
	 * dip switches on the board.  Note that the SWx registers could
	 * technically be set to force the reference clocks to match the
	 * values that the SERDES expects (or vice versa).  For now, however,
	 * we just display both values and hope the user notices when they
	 * don't match.
	 */
	puts("SERDES1 Reference : ");
	sw = QIXIS_READ(brdcfg[2]);
	clock = (sw >> 6) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 4) & 3;
	printf("Clock2 = %sMHz", freq[clock]);

	puts("\nSERDES2 Reference : ");
	clock = (sw >> 2) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 0) & 3;
	printf("Clock2 = %sMHz\n", freq[clock]);

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}
	return 66666666;
}

int config_board_mux(int ctrl_type)
{
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);

	return 0;
}

int board_init(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;

	init_final_memctl_regs();

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = env_get("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);

	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
		QIXIS_WRITE(brdcfg[9],
			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
			     FSL_QIXIS_BRDCFG9_QSPI);
#endif

	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);

#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#if CONFIG_IS_ENABLED(DM_I2C)
	rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
#else
	rtc_enable_32khz_output();
#endif
#endif

#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
	pci_init();
#endif

	return 0;
}

int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C_EARLY_INIT)
	i2c_early_init_f();
#endif
	fsl_lsch3_early_init_f();
#ifdef CONFIG_FSL_QSPI
	/* input clk: 1/2 platform clk, output: input/20 */
	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
#endif
	return 0;
}

int misc_init_r(void)
{
	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/soc/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0 &&
	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}

void board_quiesce_devices(void)
{
	fsl_mc_ldpaa_exit(gd->bd);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	fdt_fixup_memory_banks(blob, base, size, 2);

	fdt_fsl_mc_fixup_iommu_map_entry(blob);

	fsl_fdt_fixup_dr_usb(blob, bd);

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
	fdt_fixup_board_enet(blob);
	fdt_reserve_mc_mem(blob, 0x300);
#endif

	fdt_fixup_icid(blob);

	return 0;
}
#endif

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7288c2c2 YS	2	/*
7288c2c2 YS	3	* Copyright 2015 Freescale Semiconductor
8976556a	4	* Copyright 2021 NXP
7288c2c2	5	*/
d678a59d	6	#include <common.h>
2f8a6db5	7	#include <clock_legacy.h>
4e4bf944	8	#include <display_options.h>
7b51b576	9	#include <env.h>
691d719d	10	#include <init.h>
7288c2c2 YS	11	#include <malloc.h>
	12	#include <errno.h>
	13	#include <netdev.h>
	14	#include <fsl_ifc.h>
	15	#include <fsl_ddr.h>
401d1c4f	16	#include <asm/global_data.h>
7288c2c2 YS	17	#include <asm/io.h>
7288c2c2 YS	18	#include <fdt_support.h>
b08c8c48	19	#include <linux/libfdt.h>
7288c2c2	20	#include <fsl-mc/fsl_mc.h>
f3998fdc	21	#include <env_internal.h>
7288c2c2	22	#include <i2c.h>
7fb79e65	23	#include <rtc.h>
9f3183d2	24	#include <asm/arch/soc.h>
e71a980a	25	#include <hwconfig.h>
e33938ac	26	#include <asm/arch-fsl-layerscape/fsl_icid.h>
17c2a308	27	#include "../common/i2c_mux.h"
7288c2c2 YS	28
7288c2c2 YS	29	#include "../common/qixis.h"
44937214	30	#include "ls2080aqds_qixis.h"
35cc100b	31	#include "../common/vid.h"
7288c2c2	32
e71a980a HW	33	#define PIN_MUX_SEL_SDHC 0x00
e71a980a HW	34	#define PIN_MUX_SEL_DSPI 0x0a
916d9f09	35	#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
e71a980a HW	36
	37	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
	38
7288c2c2 YS	39	DECLARE_GLOBAL_DATA_PTR;
7288c2c2 YS	40
e71a980a HW	41	enum {
	42	MUX_TYPE_SDHC,
	43	MUX_TYPE_DSPI,
	44	};
	45
7288c2c2 YS	46	unsigned long long get_qixis_addr(void)
	47	{
	48	unsigned long long addr;
	49
	50	if (gd->flags & GD_FLG_RELOC)
	51	addr = QIXIS_BASE_PHYS;
	52	else
	53	addr = QIXIS_BASE_PHYS_EARLY;
	54
	55	/*
	56	* IFC address under 256MB is mapped to 0x30000000, any address above
	57	* is mapped to 0x5_10000000 up to 4GB.
	58	*/
	59	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	60
	61	return addr;
	62	}
	63
	64	int checkboard(void)
	65	{
	66	char buf[64];
	67	u8 sw;
	68	static const char *const freq[] = {"100", "125", "156.25",
	69	"100 separate SSCG"};
	70	int clock;
	71
ff1b8e3f PK	72	cpu_name(buf);
	73	printf("Board: %s-QDS, ", buf);
	74
7288c2c2	75	sw = QIXIS_READ(arch);
7288c2c2 YS	76	printf("Board Arch: V%d, ", sw >> 4);
	77	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	78
ff1b8e3f PK	79	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
ff1b8e3f PK	80
7288c2c2 YS	81	sw = QIXIS_READ(brdcfg[0]);
	82	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	83
	84	if (sw < 0x8)
	85	printf("vBank: %d\n", sw);
	86	else if (sw == 0x8)
	87	puts("PromJet\n");
	88	else if (sw == 0x9)
	89	puts("NAND\n");
a646f669 YY	90	else if (sw == 0xf)
a646f669 YY	91	puts("QSPI\n");
7288c2c2 YS	92	else if (sw == 0x15)
	93	printf("IFCCard\n");
	94	else
	95	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	96
	97	printf("FPGA: v%d (%s), build %d",
	98	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	99	(int)qixis_read_minor());
	100	/* the timestamp string contains "\n" at the end */
	101	printf(" on %s", qixis_read_time(buf));
	102
	103	/*
	104	* Display the actual SERDES reference clocks as configured by the
	105	* dip switches on the board. Note that the SWx registers could
	106	* technically be set to force the reference clocks to match the
	107	* values that the SERDES expects (or vice versa). For now, however,
	108	* we just display both values and hope the user notices when they
	109	* don't match.
	110	*/
	111	puts("SERDES1 Reference : ");
	112	sw = QIXIS_READ(brdcfg[2]);
	113	clock = (sw >> 6) & 3;
	114	printf("Clock1 = %sMHz ", freq[clock]);
	115	clock = (sw >> 4) & 3;
	116	printf("Clock2 = %sMHz", freq[clock]);
	117
	118	puts("\nSERDES2 Reference : ");
	119	clock = (sw >> 2) & 3;
	120	printf("Clock1 = %sMHz ", freq[clock]);
	121	clock = (sw >> 0) & 3;
	122	printf("Clock2 = %sMHz\n", freq[clock]);
	123
	124	return 0;
	125	}
	126
	127	unsigned long get_board_sys_clk(void)
	128	{
	129	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	130
	131	switch (sysclk_conf & 0x0F) {
	132	case QIXIS_SYSCLK_83:
	133	return 83333333;
	134	case QIXIS_SYSCLK_100:
	135	return 100000000;
	136	case QIXIS_SYSCLK_125:
	137	return 125000000;
	138	case QIXIS_SYSCLK_133:
	139	return 133333333;
	140	case QIXIS_SYSCLK_150:
	141	return 150000000;
	142	case QIXIS_SYSCLK_160:
	143	return 160000000;
	144	case QIXIS_SYSCLK_166:
	145	return 166666666;
	146	}
	147	return 66666666;
	148	}
	149
	150	unsigned long get_board_ddr_clk(void)
	151	{
	152	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	153
	154	switch ((ddrclk_conf & 0x30) >> 4) {
	155	case QIXIS_DDRCLK_100:
156	return 100000000;
157	case QIXIS_DDRCLK_125:
158	return 125000000;
159	case QIXIS_DDRCLK_133:
160	return 133333333;
161	}
162	return 66666666;
163	}
164
e71a980a HW	165	int config_board_mux(int ctrl_type)
	166	{
	167	u8 reg5;
	168
	169	reg5 = QIXIS_READ(brdcfg[5]);
	170
	171	switch (ctrl_type) {
	172	case MUX_TYPE_SDHC:
	173	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	174	break;
	175	case MUX_TYPE_DSPI:
	176	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	177	break;
	178	default:
	179	printf("Wrong mux interface type\n");
	180	return -1;
	181	}
	182
	183	QIXIS_WRITE(brdcfg[5], reg5);
	184
	185	return 0;
	186	}
	187
7288c2c2 YS	188	int board_init(void)
7288c2c2 YS	189	{
e71a980a HW	190	char *env_hwconfig;
	191	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	192	u32 val;
	193
7288c2c2 YS	194	init_final_memctl_regs();
7288c2c2 YS	195
e71a980a HW	196	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
e71a980a HW	197
00caae6d	198	env_hwconfig = env_get("hwconfig");
e71a980a HW	199
	200	if (hwconfig_f("dspi", env_hwconfig) &&
	201	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	202	config_board_mux(MUX_TYPE_DSPI);
	203	else
	204	config_board_mux(MUX_TYPE_SDHC);
	205
88718be3	206	#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
453418f2 YY	207	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
	208
	209	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
	210	QIXIS_WRITE(brdcfg[9],
	211	(QIXIS_READ(brdcfg[9]) & 0xf8) \|
	212	FSL_QIXIS_BRDCFG9_QSPI);
	213	#endif
	214
17c2a308	215	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
885ae051	216
db07c447	217	#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
2147a169	218	#if CONFIG_IS_ENABLED(DM_I2C)
65cc0e2a	219	rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
885ae051	220	#else
7fb79e65	221	rtc_enable_32khz_output();
db07c447	222	#endif
885ae051 CH	223	#endif
885ae051 CH	224
6bd026d7	225	#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
8cbef912 IC	226	pci_init();
	227	#endif
	228
7288c2c2 YS	229	return 0;
	230	}
	231
	232	int board_early_init_f(void)
	233	{
52c7e375	234	#if defined(CONFIG_SYS_I2C_EARLY_INIT)
8c77ef85 YY	235	i2c_early_init_f();
8c77ef85 YY	236	#endif
7288c2c2	237	fsl_lsch3_early_init_f();
916d9f09 YY	238	#ifdef CONFIG_FSL_QSPI
	239	/* input clk: 1/2 platform clk, output: input/20 */
	240	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
	241	#endif
7288c2c2 YS	242	return 0;
	243	}
	244
35cc100b PJ	245	int misc_init_r(void)
	246	{
	247	if (adjust_vdd(0))
	248	printf("Warning: Adjusting core voltage failed.\n");
	249
	250	return 0;
	251	}
	252
7288c2c2 YS	253	void detail_board_ddr_info(void)
	254	{
	255	puts("\nDDR ");
	256	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	257	print_ddr_info(0);
44937214	258	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a	259	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
7288c2c2 YS	260	puts("\nDP-DDR ");
	261	print_size(gd->bd->bi_dram[2].size, "");
	262	print_ddr_info(CONFIG_DP_DDR_CTRL);
	263	}
44937214	264	#endif
7288c2c2 YS	265	}
7288c2c2 YS	266
1f55a938	267	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
7288c2c2 YS	268	void fdt_fixup_board_enet(void *fdt)
	269	{
	270	int offset;
	271
e91f1dec	272	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
7288c2c2 YS	273
7288c2c2 YS	274	if (offset < 0)
e91f1dec	275	offset = fdt_path_offset(fdt, "/fsl-mc");
7288c2c2 YS	276
	277	if (offset < 0) {
	278	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	279	__func__, offset);
	280	return;
	281	}
	282
7e968049 MYK	283	if (get_mc_boot_status() == 0 &&
7e968049 MYK	284	(is_lazy_dpl_addr_valid() \|\| get_dpl_apply_status() == 0))
7288c2c2 YS	285	fdt_status_okay(fdt, offset);
	286	else
	287	fdt_status_fail(fdt, offset);
	288	}
b7b8410a AG	289
	290	void board_quiesce_devices(void)
	291	{
	292	fsl_mc_ldpaa_exit(gd->bd);
	293	}
7288c2c2 YS	294	#endif
	295
	296	#ifdef CONFIG_OF_BOARD_SETUP
b75d8dc5	297	int ft_board_setup(void blob, struct bd_info bd)
7288c2c2	298	{
a2dc818f BS	299	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	300	u64 size[CONFIG_NR_DRAM_BANKS];
7288c2c2 YS	301
	302	ft_cpu_setup(blob, bd);
	303
a2dc818f BS	304	/* fixup DT for the two GPP DDR banks */
	305	base[0] = gd->bd->bi_dram[0].start;
	306	size[0] = gd->bd->bi_dram[0].size;
	307	base[1] = gd->bd->bi_dram[1].start;
	308	size[1] = gd->bd->bi_dram[1].size;
	309
36cc0de0 YS	310	#ifdef CONFIG_RESV_RAM
	311	/* reduce size if reserved memory is within this bank */
	312	if (gd->arch.resv_ram >= base[0] &&
	313	gd->arch.resv_ram < base[0] + size[0])
	314	size[0] = gd->arch.resv_ram - base[0];
	315	else if (gd->arch.resv_ram >= base[1] &&
	316	gd->arch.resv_ram < base[1] + size[1])
	317	size[1] = gd->arch.resv_ram - base[1];
	318	#endif
	319
a2dc818f	320	fdt_fixup_memory_banks(blob, base, size, 2);
7288c2c2	321
a78df40c NG	322	fdt_fsl_mc_fixup_iommu_map_entry(blob);
a78df40c NG	323
a5c289b9	324	fsl_fdt_fixup_dr_usb(blob, bd);
ef53b8c4	325
1f55a938	326	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
7288c2c2	327	fdt_fixup_board_enet(blob);
66d885ca	328	fdt_reserve_mc_mem(blob, 0x300);
7288c2c2 YS	329	#endif
7288c2c2 YS	330
e33938ac LT	331	fdt_fixup_icid(blob);
e33938ac LT	332
7288c2c2 YS	333	return 0;
	334	}
	335	#endif
	336
	337	void qixis_dump_switch(void)
	338	{
	339	int i, nr_of_cfgsw;
	340
	341	QIXIS_WRITE(cms[0], 0x00);
	342	nr_of_cfgsw = QIXIS_READ(cms[1]);
	343
	344	puts("DIP switch settings dump:\n");
	345	for (i = 1; i <= nr_of_cfgsw; i++) {
	346	QIXIS_WRITE(cms[0], i);
	347	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	348	}
	349	}