[thirdparty/u-boot.git] / board / freescale / ls2080aqds / ls2080aqds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor
 */
#include <common.h>
#include <env.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <i2c.h>
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>


#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
#include "../common/vid.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a
#define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)

DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
	char buf[64];
	u8 sw;
	static const char *const freq[] = {"100", "125", "156.25",
					    "100 separate SSCG"};
	int clock;

	cpu_name(buf);
	printf("Board: %s-QDS, ", buf);

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);

	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x8)
		puts("PromJet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else if (sw == 0xf)
		puts("QSPI\n");
	else if (sw == 0x15)
		printf("IFCCard\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));

	/*
	 * Display the actual SERDES reference clocks as configured by the
	 * dip switches on the board.  Note that the SWx registers could
	 * technically be set to force the reference clocks to match the
	 * values that the SERDES expects (or vice versa).  For now, however,
	 * we just display both values and hope the user notices when they
	 * don't match.
	 */
	puts("SERDES1 Reference : ");
	sw = QIXIS_READ(brdcfg[2]);
	clock = (sw >> 6) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 4) & 3;
	printf("Clock2 = %sMHz", freq[clock]);

	puts("\nSERDES2 Reference : ");
	clock = (sw >> 2) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 0) & 3;
	printf("Clock2 = %sMHz\n", freq[clock]);

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}
	return 66666666;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;
#ifdef CONFIG_DM_I2C
	struct udevice *dev;

	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
	if (!ret)
		ret = dm_i2c_write(dev, 0, &ch, 1);

#else
	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int config_board_mux(int ctrl_type)
{
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);

	return 0;
}

int board_init(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;

	init_final_memctl_regs();

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = env_get("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);

	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
		QIXIS_WRITE(brdcfg[9],
			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
			     FSL_QIXIS_BRDCFG9_QSPI);
#endif

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#ifdef CONFIG_DM_I2C
	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
#else
	rtc_enable_32khz_output();
#endif
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif

	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_SYS_I2C_EARLY_INIT
	i2c_early_init_f();
#endif
	fsl_lsch3_early_init_f();
#ifdef CONFIG_FSL_QSPI
	/* input clk: 1/2 platform clk, output: input/20 */
	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
#endif
	return 0;
}

int misc_init_r(void)
{
	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
	return 0;
}
#endif

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/soc/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0 &&
	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}

void board_quiesce_devices(void)
{
	fsl_mc_ldpaa_exit(gd->bd);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	fdt_fixup_memory_banks(blob, base, size, 2);

	fdt_fsl_mc_fixup_iommu_map_entry(blob);

	fsl_fdt_fixup_dr_usb(blob, bd);

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
	fdt_fixup_board_enet(blob);
#endif

	fdt_fixup_icid(blob);

	return 0;
}
#endif

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7288c2c2 YS	2	/*
7288c2c2 YS	3	* Copyright 2015 Freescale Semiconductor
7288c2c2 YS	4	*/
7288c2c2 YS	5	#include <common.h>
7b51b576	6	#include <env.h>
7288c2c2 YS	7	#include <malloc.h>
	8	#include <errno.h>
	9	#include <netdev.h>
	10	#include <fsl_ifc.h>
	11	#include <fsl_ddr.h>
	12	#include <asm/io.h>
	13	#include <fdt_support.h>
b08c8c48	14	#include <linux/libfdt.h>
7288c2c2	15	#include <fsl-mc/fsl_mc.h>
f3998fdc	16	#include <env_internal.h>
7288c2c2	17	#include <i2c.h>
7fb79e65	18	#include <rtc.h>
9f3183d2	19	#include <asm/arch/soc.h>
e71a980a	20	#include <hwconfig.h>
fcfdb6d5	21	#include <fsl_sec.h>
54ad7b5a	22	#include <asm/arch/ppa.h>
e33938ac	23	#include <asm/arch-fsl-layerscape/fsl_icid.h>
54ad7b5a	24
7288c2c2 YS	25
7288c2c2 YS	26	#include "../common/qixis.h"
44937214	27	#include "ls2080aqds_qixis.h"
35cc100b	28	#include "../common/vid.h"
7288c2c2	29
e71a980a HW	30	#define PIN_MUX_SEL_SDHC 0x00
e71a980a HW	31	#define PIN_MUX_SEL_DSPI 0x0a
916d9f09	32	#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
e71a980a HW	33
	34	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
	35
7288c2c2 YS	36	DECLARE_GLOBAL_DATA_PTR;
7288c2c2 YS	37
e71a980a HW	38	enum {
	39	MUX_TYPE_SDHC,
	40	MUX_TYPE_DSPI,
	41	};
	42
7288c2c2 YS	43	unsigned long long get_qixis_addr(void)
	44	{
	45	unsigned long long addr;
	46
	47	if (gd->flags & GD_FLG_RELOC)
	48	addr = QIXIS_BASE_PHYS;
	49	else
	50	addr = QIXIS_BASE_PHYS_EARLY;
	51
	52	/*
	53	* IFC address under 256MB is mapped to 0x30000000, any address above
	54	* is mapped to 0x5_10000000 up to 4GB.
	55	*/
	56	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	57
	58	return addr;
	59	}
	60
	61	int checkboard(void)
	62	{
	63	char buf[64];
	64	u8 sw;
	65	static const char *const freq[] = {"100", "125", "156.25",
	66	"100 separate SSCG"};
	67	int clock;
	68
ff1b8e3f PK	69	cpu_name(buf);
	70	printf("Board: %s-QDS, ", buf);
	71
7288c2c2	72	sw = QIXIS_READ(arch);
7288c2c2 YS	73	printf("Board Arch: V%d, ", sw >> 4);
	74	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	75
ff1b8e3f PK	76	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
ff1b8e3f PK	77
7288c2c2 YS	78	sw = QIXIS_READ(brdcfg[0]);
	79	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	80
	81	if (sw < 0x8)
	82	printf("vBank: %d\n", sw);
	83	else if (sw == 0x8)
	84	puts("PromJet\n");
	85	else if (sw == 0x9)
	86	puts("NAND\n");
a646f669 YY	87	else if (sw == 0xf)
a646f669 YY	88	puts("QSPI\n");
7288c2c2 YS	89	else if (sw == 0x15)
	90	printf("IFCCard\n");
	91	else
	92	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	93
	94	printf("FPGA: v%d (%s), build %d",
	95	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	96	(int)qixis_read_minor());
	97	/* the timestamp string contains "\n" at the end */
	98	printf(" on %s", qixis_read_time(buf));
	99
	100	/*
	101	* Display the actual SERDES reference clocks as configured by the
	102	* dip switches on the board. Note that the SWx registers could
	103	* technically be set to force the reference clocks to match the
	104	* values that the SERDES expects (or vice versa). For now, however,
	105	* we just display both values and hope the user notices when they
	106	* don't match.
	107	*/
	108	puts("SERDES1 Reference : ");
	109	sw = QIXIS_READ(brdcfg[2]);
	110	clock = (sw >> 6) & 3;
	111	printf("Clock1 = %sMHz ", freq[clock]);
	112	clock = (sw >> 4) & 3;
	113	printf("Clock2 = %sMHz", freq[clock]);
	114
	115	puts("\nSERDES2 Reference : ");
	116	clock = (sw >> 2) & 3;
	117	printf("Clock1 = %sMHz ", freq[clock]);
	118	clock = (sw >> 0) & 3;
	119	printf("Clock2 = %sMHz\n", freq[clock]);
	120
	121	return 0;
	122	}
	123
	124	unsigned long get_board_sys_clk(void)
	125	{
	126	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	127
	128	switch (sysclk_conf & 0x0F) {
	129	case QIXIS_SYSCLK_83:
	130	return 83333333;
	131	case QIXIS_SYSCLK_100:
	132	return 100000000;
	133	case QIXIS_SYSCLK_125:
	134	return 125000000;
	135	case QIXIS_SYSCLK_133:
	136	return 133333333;
	137	case QIXIS_SYSCLK_150:
	138	return 150000000;
	139	case QIXIS_SYSCLK_160:
	140	return 160000000;
	141	case QIXIS_SYSCLK_166:
	142	return 166666666;
	143	}
	144	return 66666666;
	145	}
	146
	147	unsigned long get_board_ddr_clk(void)
	148	{
	149	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	150
	151	switch ((ddrclk_conf & 0x30) >> 4) {
	152	case QIXIS_DDRCLK_100:
153	return 100000000;
154	case QIXIS_DDRCLK_125:
155	return 125000000;
156	case QIXIS_DDRCLK_133:
157	return 133333333;
158	}
159	return 66666666;
160	}
161
162	int select_i2c_ch_pca9547(u8 ch)
163	{
164	int ret;
885ae051 CH	165	#ifdef CONFIG_DM_I2C
885ae051 CH	166	struct udevice *dev;
7288c2c2	167
885ae051 CH	168	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
	169	if (!ret)
	170	ret = dm_i2c_write(dev, 0, &ch, 1);
	171
	172	#else
7288c2c2	173	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
885ae051	174	#endif
7288c2c2 YS	175	if (ret) {
	176	puts("PCA: failed to select proper channel\n");
	177	return ret;
	178	}
	179
	180	return 0;
	181	}
	182
e71a980a HW	183	int config_board_mux(int ctrl_type)
	184	{
	185	u8 reg5;
	186
	187	reg5 = QIXIS_READ(brdcfg[5]);
	188
	189	switch (ctrl_type) {
	190	case MUX_TYPE_SDHC:
	191	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	192	break;
	193	case MUX_TYPE_DSPI:
	194	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	195	break;
	196	default:
	197	printf("Wrong mux interface type\n");
	198	return -1;
	199	}
	200
	201	QIXIS_WRITE(brdcfg[5], reg5);
	202
	203	return 0;
	204	}
	205
7288c2c2 YS	206	int board_init(void)
7288c2c2 YS	207	{
e71a980a HW	208	char *env_hwconfig;
	209	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	210	u32 val;
	211
7288c2c2 YS	212	init_final_memctl_regs();
7288c2c2 YS	213
e71a980a HW	214	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
e71a980a HW	215
00caae6d	216	env_hwconfig = env_get("hwconfig");
e71a980a HW	217
	218	if (hwconfig_f("dspi", env_hwconfig) &&
	219	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	220	config_board_mux(MUX_TYPE_DSPI);
	221	else
	222	config_board_mux(MUX_TYPE_SDHC);
	223
453418f2 YY	224	#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
	225	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
	226
	227	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
	228	QIXIS_WRITE(brdcfg[9],
	229	(QIXIS_READ(brdcfg[9]) & 0xf8) \|
	230	FSL_QIXIS_BRDCFG9_QSPI);
	231	#endif
	232
7288c2c2 YS	233	#ifdef CONFIG_ENV_IS_NOWHERE
	234	gd->env_addr = (ulong)&default_environment[0];
	235	#endif
	236	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
885ae051	237
db07c447	238	#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
885ae051 CH	239	#ifdef CONFIG_DM_I2C
	240	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
	241	#else
7fb79e65	242	rtc_enable_32khz_output();
db07c447	243	#endif
885ae051 CH	244	#endif
885ae051 CH	245
15e7c681 UA	246	#ifdef CONFIG_FSL_CAAM
	247	sec_init();
	248	#endif
54ad7b5a SK	249
	250	#ifdef CONFIG_FSL_LS_PPA
	251	ppa_init();
	252	#endif
	253
7288c2c2 YS	254	return 0;
	255	}
	256
	257	int board_early_init_f(void)
	258	{
8c77ef85 YY	259	#ifdef CONFIG_SYS_I2C_EARLY_INIT
	260	i2c_early_init_f();
	261	#endif
7288c2c2	262	fsl_lsch3_early_init_f();
916d9f09 YY	263	#ifdef CONFIG_FSL_QSPI
	264	/* input clk: 1/2 platform clk, output: input/20 */
	265	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
	266	#endif
7288c2c2 YS	267	return 0;
	268	}
	269
35cc100b PJ	270	int misc_init_r(void)
	271	{
	272	if (adjust_vdd(0))
	273	printf("Warning: Adjusting core voltage failed.\n");
	274
	275	return 0;
	276	}
	277
7288c2c2 YS	278	void detail_board_ddr_info(void)
	279	{
	280	puts("\nDDR ");
	281	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	282	print_ddr_info(0);
44937214	283	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a	284	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
7288c2c2 YS	285	puts("\nDP-DDR ");
	286	print_size(gd->bd->bi_dram[2].size, "");
	287	print_ddr_info(CONFIG_DP_DDR_CTRL);
	288	}
44937214	289	#endif
7288c2c2 YS	290	}
7288c2c2 YS	291
7288c2c2 YS	292	#if defined(CONFIG_ARCH_MISC_INIT)
	293	int arch_misc_init(void)
	294	{
7288c2c2 YS	295	return 0;
	296	}
	297	#endif
	298
1f55a938	299	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
7288c2c2 YS	300	void fdt_fixup_board_enet(void *fdt)
	301	{
	302	int offset;
	303
e91f1dec	304	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
7288c2c2 YS	305
7288c2c2 YS	306	if (offset < 0)
e91f1dec	307	offset = fdt_path_offset(fdt, "/fsl-mc");
7288c2c2 YS	308
	309	if (offset < 0) {
	310	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	311	__func__, offset);
	312	return;
	313	}
	314
7e968049 MYK	315	if (get_mc_boot_status() == 0 &&
7e968049 MYK	316	(is_lazy_dpl_addr_valid() \|\| get_dpl_apply_status() == 0))
7288c2c2 YS	317	fdt_status_okay(fdt, offset);
	318	else
	319	fdt_status_fail(fdt, offset);
	320	}
b7b8410a AG	321
	322	void board_quiesce_devices(void)
	323	{
	324	fsl_mc_ldpaa_exit(gd->bd);
	325	}
7288c2c2 YS	326	#endif
	327
	328	#ifdef CONFIG_OF_BOARD_SETUP
	329	int ft_board_setup(void blob, bd_t bd)
	330	{
a2dc818f BS	331	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	332	u64 size[CONFIG_NR_DRAM_BANKS];
7288c2c2 YS	333
	334	ft_cpu_setup(blob, bd);
	335
a2dc818f BS	336	/* fixup DT for the two GPP DDR banks */
	337	base[0] = gd->bd->bi_dram[0].start;
	338	size[0] = gd->bd->bi_dram[0].size;
	339	base[1] = gd->bd->bi_dram[1].start;
	340	size[1] = gd->bd->bi_dram[1].size;
	341
36cc0de0 YS	342	#ifdef CONFIG_RESV_RAM
	343	/* reduce size if reserved memory is within this bank */
	344	if (gd->arch.resv_ram >= base[0] &&
	345	gd->arch.resv_ram < base[0] + size[0])
	346	size[0] = gd->arch.resv_ram - base[0];
	347	else if (gd->arch.resv_ram >= base[1] &&
	348	gd->arch.resv_ram < base[1] + size[1])
	349	size[1] = gd->arch.resv_ram - base[1];
	350	#endif
	351
a2dc818f	352	fdt_fixup_memory_banks(blob, base, size, 2);
7288c2c2	353
a78df40c NG	354	fdt_fsl_mc_fixup_iommu_map_entry(blob);
a78df40c NG	355
a5c289b9	356	fsl_fdt_fixup_dr_usb(blob, bd);
ef53b8c4	357
1f55a938	358	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
7288c2c2	359	fdt_fixup_board_enet(blob);
7288c2c2 YS	360	#endif
7288c2c2 YS	361
e33938ac LT	362	fdt_fixup_icid(blob);
e33938ac LT	363
7288c2c2 YS	364	return 0;
	365	}
	366	#endif
	367
	368	void qixis_dump_switch(void)
	369	{
	370	int i, nr_of_cfgsw;
	371
	372	QIXIS_WRITE(cms[0], 0x00);
	373	nr_of_cfgsw = QIXIS_READ(cms[1]);
	374
	375	puts("DIP switch settings dump:\n");
	376	for (i = 1; i <= nr_of_cfgsw; i++) {
	377	QIXIS_WRITE(cms[0], i);
	378	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	379	}
	380	}