[people/ms/u-boot.git] / board / freescale / m5275evb / mii.c

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/fec.h>
#include <asm/immap.h>

#include <config.h>
#include <net.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG

int fecpin_setclear(struct eth_device *dev, int setclear)
{
	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;

	if (setclear) {
		/* Enable Ethernet pins */
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
			gpio->par_feci2c |= 0x0F00;
			gpio->par_fec0hl |= 0xC0;
		} else {
			gpio->par_feci2c |= 0x00A0;
			gpio->par_fec1hl |= 0xC0;
		}
	} else {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
			gpio->par_feci2c &= ~0x0F00;
			gpio->par_fec0hl &= ~0xC0;
		} else {
			gpio->par_feci2c &= ~0x00A0;
			gpio->par_fec1hl &= ~0xC0;
		}
	}

	return 0;
}

#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>

/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))

#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))

/* PHY identification */
#define PHY_ID_LXT970		0x78100000	/* LXT970 */
#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
#define PHY_ID_QS6612		0x01814400	/* QS6612 */
#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
#define PHY_ID_KS8721BL		0x00221619	/* Micrel KS8721BL/SL */

#define STR_ID_LXT970		"LXT970"
#define STR_ID_LXT971		"LXT971"
#define STR_ID_82555		"Intel82555"
#define STR_ID_QS6612		"QS6612"
#define STR_ID_AMD79C784	"AMD79C784"
#define STR_ID_LSI80225		"LSI80225"
#define STR_ID_LSI80225B	"LSI80225/B"
#define STR_ID_DP83848VV	"N83848"
#define STR_ID_DP83849		"N83849"
#define STR_ID_KS8721BL		"KS8721BL"

/****************************************************************************
 * mii_init -- Initialize the MII for MII command without ethernet
 * This function is a subset of eth_init
 ****************************************************************************
 */
void mii_reset(struct fec_info_s *info)
{
	volatile fec_t *fecp = (fec_t *) (info->miibase);
	int i;

	fecp->ecr = FEC_ECR_RESET;
	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
		udelay(1);
	}
	if (i == FEC_RESET_DELAY) {
		printf("FEC_RESET_DELAY timeout\n");
	}
}

/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
	struct fec_info_s *info;
	struct eth_device *dev;
	volatile fec_t *ep;
	uint mii_reply;
	int j = 0;

	/* retrieve from register structure */
	dev = eth_get_dev();
	info = dev->priv;

	ep = (fec_t *) info->miibase;

	ep->mmfr = mii_cmd;	/* command to phy */

	/* wait for mii complete */
	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
		udelay(1);
		j++;
	}
	if (j >= MCFFEC_TOUT_LOOP) {
		printf("MII not complete\n");
		return -1;
	}

	mii_reply = ep->mmfr;	/* result from phy */
	ep->eir = FEC_EIR_MII;	/* clear MII complete */
#ifdef ET_DEBUG
	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif

	return (mii_reply & 0xffff);	/* data read from phy */
}
#endif	/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */

#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
	struct fec_info_s *info = dev->priv;
	int phyaddr, pass;
	uint phyno, phytype;

	if (info->phyname_init)
		return info->phy_addr;

	phyaddr = -1;		/* didn't find a PHY yet */
	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
		if (pass > 1) {
			/* PHY may need more time to recover from reset.
			 * The LXT970 needs 50ms typical, no maximum is
			 * specified, so wait 10ms before try again.
			 * With 11 passes this gives it 100ms to wake up.
			 */
			udelay(10000);	/* wait 10ms */
		}

		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {

			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
			printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
			if (phytype != 0xffff) {
				phyaddr = phyno;
				phytype <<= 16;
				phytype |=
				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));

				switch (phytype & 0xffffffff) {
				case PHY_ID_KS8721BL:
					strcpy(info->phy_name,
					       STR_ID_KS8721BL);
					info->phyname_init = 1;
					break;
				default:
					strcpy(info->phy_name, "unknown");
					info->phyname_init = 1;
					break;
				}

#ifdef ET_DEBUG
				printf("PHY @ 0x%x pass %d type ", phyno, pass);
				switch (phytype & 0xffffffff) {
				case PHY_ID_KS8721BL:
					printf(STR_ID_KS8721BL);
					break;
				default:
					printf("0x%08x\n", phytype);
					break;
				}
#endif
			}
		}
	}
	if (phyaddr < 0)
		printf("No PHY device found.\n");

	return phyaddr;
}
#endif				/* CONFIG_SYS_DISCOVER_PHY */

void mii_init(void) __attribute__((weak,alias("__mii_init")));

void __mii_init(void)
{
	volatile fec_t *fecp;
	struct fec_info_s *info;
	struct eth_device *dev;
	int miispd = 0, i = 0;
	u16 autoneg = 0;

	/* retrieve from register structure */
	dev = eth_get_dev();
	info = dev->priv;

	fecp = (fec_t *) info->miibase;

	fecpin_setclear(dev, 1);

	mii_reset(info);

	/* We use strictly polling mode only */
	fecp->eimr = 0;

	/* Clear any pending interrupt */
	fecp->eir = 0xffffffff;

	/* Set MII speed */
	miispd = (gd->bus_clk / 1000000) / 5;
	fecp->mscr = miispd << 1;

	info->phy_addr = mii_discover_phy(dev);

#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
	while (i < MCFFEC_TOUT_LOOP) {
		autoneg = 0;
		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
		i++;

		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
			break;

		udelay(500);
	}
	if (i >= MCFFEC_TOUT_LOOP) {
		printf("Auto Negotiation not complete\n");
	}

	/* adapt to the half/full speed settings */
	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}

/*****************************************************************************
 * Read and write a MII PHY register, routines used by MII Utilities
 *
 * FIXME: These routines are expected to return 0 on success, but mii_send
 *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 *	  no PHY connected...
 *	  For now always return 0.
 * FIXME: These routines only work after calling eth_init() at least once!
 *	  Otherwise they hang in mii_send() !!! Sorry!
 *****************************************************************************/

int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
		       unsigned short *value)
{
	short rdreg;		/* register working value */

#ifdef MII_DEBUG
	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
	rdreg = mii_send(mk_mii_read(addr, reg));

	*value = rdreg;

#ifdef MII_DEBUG
	printf("0x%04x\n", *value);
#endif

	return 0;
}

int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
			unsigned short value)
{
	short rdreg;		/* register working value */

#ifdef MII_DEBUG
	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif

	rdreg = mii_send(mk_mii_write(addr, reg, value));

#ifdef MII_DEBUG
	printf("0x%04x\n", value);
#endif

	return 0;
}

#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
Commit	Line	Data
545c8e0a MF	1	/*
	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/fec.h>
	26	#include <asm/immap.h>
	27
	28	#include <config.h>
	29	#include <net.h>
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
	34	#undef MII_DEBUG
	35	#undef ET_DEBUG
	36
	37	int fecpin_setclear(struct eth_device *dev, int setclear)
	38	{
	39	struct fec_info_s info = (struct fec_info_s ) dev->priv;
	40	volatile gpio_t gpio = (gpio_t )MMAP_GPIO;
	41
	42	if (setclear) {
	43	/* Enable Ethernet pins */
6d0f6bcf	44	if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
545c8e0a MF	45	gpio->par_feci2c \|= 0x0F00;
	46	gpio->par_fec0hl \|= 0xC0;
	47	} else {
	48	gpio->par_feci2c \|= 0x00A0;
	49	gpio->par_fec1hl \|= 0xC0;
	50	}
	51	} else {
6d0f6bcf	52	if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
1aeed8d7 WD	53	gpio->par_feci2c &= ~0x0F00;
1aeed8d7 WD	54	gpio->par_fec0hl &= ~0xC0;
545c8e0a	55	} else {
1aeed8d7 WD	56	gpio->par_feci2c &= ~0x00A0;
1aeed8d7 WD	57	gpio->par_fec1hl &= ~0xC0;
545c8e0a MF	58	}
	59	}
	60
	61	return 0;
	62	}
	63
6d0f6bcf	64	#if defined(CONFIG_SYS_DISCOVER_PHY) \|\| defined(CONFIG_CMD_MII)
545c8e0a MF	65	#include <miiphy.h>
	66
	67	/* Make MII read/write commands for the FEC. */
	68	#define mk_mii_read(ADDR, REG) (0x60020000 \| ((ADDR << 23) \| (REG & 0x1f) << 18))
	69
	70	#define mk_mii_write(ADDR, REG, VAL) (0x50020000 \| ((ADDR << 23) \| (REG & 0x1f) << 18) \| (VAL & 0xffff))
	71
	72	/* PHY identification */
	73	#define PHY_ID_LXT970 0x78100000 /* LXT970 */
	74	#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
	75	#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
	76	#define PHY_ID_QS6612 0x01814400 /* QS6612 */
	77	#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
	78	#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
	79	#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
	80	#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
	81	#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
	82	#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
	83
	84	#define STR_ID_LXT970 "LXT970"
	85	#define STR_ID_LXT971 "LXT971"
	86	#define STR_ID_82555 "Intel82555"
	87	#define STR_ID_QS6612 "QS6612"
	88	#define STR_ID_AMD79C784 "AMD79C784"
	89	#define STR_ID_LSI80225 "LSI80225"
	90	#define STR_ID_LSI80225B "LSI80225/B"
	91	#define STR_ID_DP83848VV "N83848"
	92	#define STR_ID_DP83849 "N83849"
	93	#define STR_ID_KS8721BL "KS8721BL"
	94
	95	/****************************************************************************
	96	* mii_init -- Initialize the MII for MII command without ethernet
	97	* This function is a subset of eth_init
	98	****************************************************************************
	99	*/
	100	void mii_reset(struct fec_info_s *info)
	101	{
	102	volatile fec_t fecp = (fec_t ) (info->miibase);
	103	int i;
	104
	105	fecp->ecr = FEC_ECR_RESET;
	106	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
	107	udelay(1);
	108	}
	109	if (i == FEC_RESET_DELAY) {
	110	printf("FEC_RESET_DELAY timeout\n");
	111	}
	112	}
	113
	114	/* send command to phy using mii, wait for result */
	115	uint mii_send(uint mii_cmd)
	116	{
	117	struct fec_info_s *info;
	118	struct eth_device *dev;
	119	volatile fec_t *ep;
	120	uint mii_reply;
	121	int j = 0;
	122
	123	/* retrieve from register structure */
	124	dev = eth_get_dev();
	125	info = dev->priv;
	126
	127	ep = (fec_t *) info->miibase;
	128
129	ep->mmfr = mii_cmd; /* command to phy */
130
131	/* wait for mii complete */
132	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
133	udelay(1);
134	j++;
135	}
136	if (j >= MCFFEC_TOUT_LOOP) {
137	printf("MII not complete\n");
138	return -1;
139	}
140
141	mii_reply = ep->mmfr; /* result from phy */
142	ep->eir = FEC_EIR_MII; /* clear MII complete */
143	#ifdef ET_DEBUG
144	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
145	__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
146	#endif
147
148	return (mii_reply & 0xffff); /* data read from phy */
149	}
6d0f6bcf	150	#endif /* CONFIG_SYS_DISCOVER_PHY \|\| (CONFIG_COMMANDS & CONFIG_CMD_MII) */
545c8e0a	151
6d0f6bcf	152	#if defined(CONFIG_SYS_DISCOVER_PHY)
545c8e0a MF	153	int mii_discover_phy(struct eth_device *dev)
	154	{
	155	#define MAX_PHY_PASSES 11
	156	struct fec_info_s *info = dev->priv;
	157	int phyaddr, pass;
	158	uint phyno, phytype;
	159
	160	if (info->phyname_init)
	161	return info->phy_addr;
	162
	163	phyaddr = -1; /* didn't find a PHY yet */
	164	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
	165	if (pass > 1) {
	166	/* PHY may need more time to recover from reset.
	167	* The LXT970 needs 50ms typical, no maximum is
	168	* specified, so wait 10ms before try again.
	169	* With 11 passes this gives it 100ms to wake up.
	170	*/
	171	udelay(10000); /* wait 10ms */
	172	}
	173
	174	for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
	175
	176	phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
	177	#ifdef ET_DEBUG
	178	printf("PHY type 0x%x pass %d type\n", phytype, pass);
	179	#endif
	180	if (phytype != 0xffff) {
	181	phyaddr = phyno;
	182	phytype <<= 16;
	183	phytype \|=
	184	mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
	185
	186	switch (phytype & 0xffffffff) {
	187	case PHY_ID_KS8721BL:
	188	strcpy(info->phy_name,
	189	STR_ID_KS8721BL);
	190	info->phyname_init = 1;
	191	break;
	192	default:
	193	strcpy(info->phy_name, "unknown");
	194	info->phyname_init = 1;
	195	break;
	196	}
	197
	198	#ifdef ET_DEBUG
	199	printf("PHY @ 0x%x pass %d type ", phyno, pass);
	200	switch (phytype & 0xffffffff) {
	201	case PHY_ID_KS8721BL:
	202	printf(STR_ID_KS8721BL);
	203	break;
	204	default:
	205	printf("0x%08x\n", phytype);
	206	break;
	207	}
	208	#endif
	209	}
	210	}
	211	}
	212	if (phyaddr < 0)
	213	printf("No PHY device found.\n");
	214
	215	return phyaddr;
	216	}
6d0f6bcf	217	#endif /* CONFIG_SYS_DISCOVER_PHY */
545c8e0a MF	218
	219	void mii_init(void) __attribute__((weak,alias("__mii_init")));
	220
	221	void __mii_init(void)
	222	{
	223	volatile fec_t *fecp;
	224	struct fec_info_s *info;
	225	struct eth_device *dev;
	226	int miispd = 0, i = 0;
	227	u16 autoneg = 0;
	228
	229	/* retrieve from register structure */
	230	dev = eth_get_dev();
	231	info = dev->priv;
	232
	233	fecp = (fec_t *) info->miibase;
	234
	235	fecpin_setclear(dev, 1);
	236
	237	mii_reset(info);
	238
	239	/* We use strictly polling mode only */
	240	fecp->eimr = 0;
	241
	242	/* Clear any pending interrupt */
	243	fecp->eir = 0xffffffff;
	244
	245	/* Set MII speed */
	246	miispd = (gd->bus_clk / 1000000) / 5;
	247	fecp->mscr = miispd << 1;
	248
	249	info->phy_addr = mii_discover_phy(dev);
	250
	251	#define AUTONEGLINK (PHY_BMSR_AUTN_COMP \| PHY_BMSR_LS)
	252	while (i < MCFFEC_TOUT_LOOP) {
	253	autoneg = 0;
	254	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
	255	i++;
	256
	257	if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
	258	break;
	259
	260	udelay(500);
	261	}
	262	if (i >= MCFFEC_TOUT_LOOP) {
	263	printf("Auto Negotiation not complete\n");
	264	}
	265
	266	/* adapt to the half/full speed settings */
	267	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
	268	info->dup_spd \|= miiphy_speed(dev->name, info->phy_addr);
	269	}
	270
	271	/*****************************************************************************
	272	* Read and write a MII PHY register, routines used by MII Utilities
	273	*
	274	* FIXME: These routines are expected to return 0 on success, but mii_send
	275	* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
	276	* no PHY connected...
	277	* For now always return 0.
	278	* FIXME: These routines only work after calling eth_init() at least once!
	279	* Otherwise they hang in mii_send() !!! Sorry!
	280	*****************************************************************************/
	281
282	int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
283	unsigned short *value)
284	{
285	short rdreg; /* register working value */
286
287	#ifdef MII_DEBUG
288	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
289	#endif
290	rdreg = mii_send(mk_mii_read(addr, reg));
291
292	*value = rdreg;
293
294	#ifdef MII_DEBUG
295	printf("0x%04x\n", *value);
296	#endif
297
298	return 0;
299	}
300
301	int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
302	unsigned short value)
303	{
304	short rdreg; /* register working value */
305
306	#ifdef MII_DEBUG
307	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
308	#endif
309
310	rdreg = mii_send(mk_mii_write(addr, reg, value));
311
312	#ifdef MII_DEBUG
313	printf("0x%04x\n", value);
314	#endif
315
316	return 0;
317	}
318
319	#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */