[people/ms/u-boot.git] / board / freescale / m5329evb / m5329evb.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/fec.h>
#include <asm/m5329.h>
#include <asm/immap_5329.h>

#include <config.h>
#include <net.h>

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	puts("Board: ");
	puts("Freescale FireEngine 5329 EVB\n");
	return 0;
};

long int initdram(int board_type)
{
	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
	u32 dramsize, i;

	dramsize = CFG_SDRAM_SIZE * 0x100000;

	for (i = 0x13; i < 0x20; i++) {
		if (dramsize == (1 << i))
			break;
	}
	i--;

	sdram->cs0 = (CFG_SDRAM_BASE | i);
	sdram->cfg1 = CFG_SDRAM_CFG1;
	sdram->cfg2 = CFG_SDRAM_CFG2;

	/* Issue PALL */
	sdram->ctrl = CFG_SDRAM_CTRL | 2;

	/* Issue LEMR */
	sdram->mode = CFG_SDRAM_EMOD;
	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);

	udelay(500);

	/* Issue PALL */
	sdram->ctrl = (CFG_SDRAM_CTRL | 2);

	/* Perform two refresh cycles */
	sdram->ctrl = CFG_SDRAM_CTRL | 4;
	sdram->ctrl = CFG_SDRAM_CTRL | 4;

	sdram->mode = CFG_SDRAM_MODE;

	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;

	udelay(100);

	return dramsize;
};

int testdram(void)
{
	/* TODO: XXX XXX XXX */
	printf("DRAM test not implemented!\n");

	return (0);
}

#ifdef CFG_FLASH_CFI
void sync(void)
{
	/* This sync function is PowerPC intruction,
	   coldfire does not have this instruction. Dummy function */
}
#endif

#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
#undef MII_DEBUG
#undef ET_DEBUG

int fecpin_setclear(struct eth_device *dev, int setclear)
{
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if (setclear) {
		gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
		gpio->par_feci2c |=
		    GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
	} else {
		gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
		gpio->par_feci2c &=
		    ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
	}
	return 0;
}

#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
#include <miiphy.h>

/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | \
						(REG & 0x1f) << 18))

#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
						(REG & 0x1f) << 18) | \
						(VAL & 0xffff))

/* PHY identification */
#define PHY_ID_LXT970		0x78100000	/* LXT970 */
#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
#define PHY_ID_QS6612		0x01814400	/* QS6612 */
#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */

#define STR_ID_LXT970		"LXT970"
#define STR_ID_LXT971		"LXT971"
#define STR_ID_82555		"Intel82555"
#define STR_ID_QS6612		"QS6612"
#define STR_ID_AMD79C784	"AMD79C784"
#define STR_ID_LSI80225		"LSI80225"
#define STR_ID_LSI80225B	"LSI80225/B"
#define STR_ID_DP83848VV	"N83848"
#define STR_ID_DP83849		"N83849"

/****************************************************************************
 * mii_init -- Initialize the MII for MII command without ethernet
 * This function is a subset of eth_init
 ****************************************************************************
 */
void mii_reset(struct fec_info_s *info)
{
	volatile fec_t *fecp = (fec_t *) (info->miibase);
	int i;

	fecp->ecr = FEC_ECR_RESET;
	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
		udelay(1);
	}
	if (i == FEC_RESET_DELAY) {
		printf("FEC_RESET_DELAY timeout\n");
	}
}

/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
	struct fec_info_s *info;
	struct eth_device *dev;
	volatile fec_t *ep;
	uint mii_reply;
	int j = 0;

	/* retrieve from register structure */
	dev = eth_get_dev();
	info = dev->priv;

	ep = (fec_t *) info->miibase;

	ep->mmfr = mii_cmd;	/* command to phy */

	/* wait for mii complete */
	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
		udelay(1);
		j++;
	}
	if (j >= MCFFEC_TOUT_LOOP) {
		printf("MII not complete\n");
		return -1;
	}

	mii_reply = ep->mmfr;	/* result from phy */
	ep->eir = FEC_EIR_MII;	/* clear MII complete */
#ifdef ET_DEBUG
	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif

	return (mii_reply & 0xffff);	/* data read from phy */
}
#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */

#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
	struct fec_info_s *info = dev->priv;
	int phyaddr, pass;
	uint phyno, phytype;

	if (info->phyname_init)
		return info->phy_addr;

	phyaddr = -1;		/* didn't find a PHY yet */
	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
		if (pass > 1) {
			/* PHY may need more time to recover from reset.
			 * The LXT970 needs 50ms typical, no maximum is
			 * specified, so wait 10ms before try again.
			 * With 11 passes this gives it 100ms to wake up.
			 */
			udelay(10000);	/* wait 10ms */
		}

		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {

			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
			printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
			if (phytype != 0xffff) {
				phyaddr = phyno;
				phytype <<= 16;
				phytype |=
				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));

				switch (phytype & 0xffffffff) {
				case PHY_ID_DP83848VV:
					strcpy(info->phy_name,
					       STR_ID_DP83848VV);
					info->phyname_init = 1;
					break;
				default:
					strcpy(info->phy_name, "unknown");
					info->phyname_init = 1;
					break;
				}

#ifdef ET_DEBUG
				printf("PHY @ 0x%x pass %d type ", phyno, pass);
				switch (phytype & 0xffffffff) {
				case PHY_ID_DP83848VV:
					printf(STR_ID_DP83848VV);
					break;
				default:
					printf("0x%08x\n", phytype);
					break;
				}
#endif
			}
		}
	}
	if (phyaddr < 0)
		printf("No PHY device found.\n");

	return phyaddr;
}
#endif				/* CFG_DISCOVER_PHY */

void mii_init(void)
{
	volatile fec_t *fecp;
	struct fec_info_s *info;
	struct eth_device *dev;
	int miispd = 0, i = 0;
	u16 autoneg = 0;

	/* retrieve from register structure */
	dev = eth_get_dev();
	info = dev->priv;

	fecp = (fec_t *) info->miibase;

	fecpin_setclear(dev, 1);

	mii_reset(info);

	/* We use strictly polling mode only */
	fecp->eimr = 0;

	/* Clear any pending interrupt */
	fecp->eir = 0xffffffff;

	/* Set MII speed */
	miispd = (gd->bus_clk / 1000000) / 5;
	fecp->mscr = miispd << 1;

	info->phy_addr = mii_discover_phy(dev);

#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
	while (i < MCFFEC_TOUT_LOOP) {
		autoneg = 0;
		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
		i++;

		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
			break;

		udelay(500);
	}
	if (i >= MCFFEC_TOUT_LOOP) {
		printf("Auto Negotiation not complete\n");
	}

	/* adapt to the half/full speed settings */
	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}

/*****************************************************************************
 * Read and write a MII PHY register, routines used by MII Utilities
 *
 * FIXME: These routines are expected to return 0 on success, but mii_send
 *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 *	  no PHY connected...
 *	  For now always return 0.
 * FIXME: These routines only work after calling eth_init() at least once!
 *	  Otherwise they hang in mii_send() !!! Sorry!
 *****************************************************************************/

int mcffec_miiphy_read(char *devname, unsigned char addr,
		       unsigned char reg, unsigned short *value)
{
	short rdreg;		/* register working value */

#ifdef MII_DEBUG
	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
	rdreg = mii_send(mk_mii_read(addr, reg));

	*value = rdreg;

#ifdef MII_DEBUG
	printf("0x%04x\n", *value);
#endif

	return 0;
}

int mcffec_miiphy_write(char *devname, unsigned char addr,
			unsigned char reg, unsigned short value)
{
	short rdreg;		/* register working value */

#ifdef MII_DEBUG
	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif

	rdreg = mii_send(mk_mii_write(addr, reg, value));

#ifdef MII_DEBUG
	printf("0x%04x\n", value);
#endif

	return 0;
}

#endif				/* CFG_CMD_NET, FEC_ENET & NET_MULTI */
Commit	Line	Data
8e585f02 TL	1	/*
	2	* (C) Copyright 2000-2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <asm/fec.h>
	29	#include <asm/m5329.h>
	30	#include <asm/immap_5329.h>
	31
	32	#include <config.h>
	33	#include <net.h>
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
	37	int checkboard(void)
	38	{
	39	puts("Board: ");
	40	puts("Freescale FireEngine 5329 EVB\n");
	41	return 0;
	42	};
	43
	44	long int initdram(int board_type)
	45	{
	46	volatile sdram_t sdram = (volatile sdram_t )(MMAP_SDRAM);
	47	u32 dramsize, i;
	48
	49	dramsize = CFG_SDRAM_SIZE * 0x100000;
	50
	51	for (i = 0x13; i < 0x20; i++) {
	52	if (dramsize == (1 << i))
	53	break;
	54	}
	55	i--;
	56
	57	sdram->cs0 = (CFG_SDRAM_BASE \| i);
	58	sdram->cfg1 = CFG_SDRAM_CFG1;
	59	sdram->cfg2 = CFG_SDRAM_CFG2;
	60
	61	/* Issue PALL */
	62	sdram->ctrl = CFG_SDRAM_CTRL \| 2;
	63
	64	/* Issue LEMR */
65	sdram->mode = CFG_SDRAM_EMOD;
66	sdram->mode = (CFG_SDRAM_MODE \| 0x04000000);
67
68	udelay(500);
69
70	/* Issue PALL */
71	sdram->ctrl = (CFG_SDRAM_CTRL \| 2);
72
73	/* Perform two refresh cycles */
74	sdram->ctrl = CFG_SDRAM_CTRL \| 4;
75	sdram->ctrl = CFG_SDRAM_CTRL \| 4;
76
77	sdram->mode = CFG_SDRAM_MODE;
78
79	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) \| 0x10000c00;
80
81	udelay(100);
82
83	return dramsize;
84	};
85
86	int testdram(void)
87	{
88	/* TODO: XXX XXX XXX */
89	printf("DRAM test not implemented!\n");
90
91	return (0);
92	}
93
94	#ifdef CFG_FLASH_CFI
95	void sync(void)
96	{
97	/* This sync function is PowerPC intruction,
98	coldfire does not have this instruction. Dummy function */
99	}
100	#endif
101
102	#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
103	#undef MII_DEBUG
104	#undef ET_DEBUG
105
106	int fecpin_setclear(struct eth_device *dev, int setclear)
107	{
108	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
109
110	if (setclear) {
111	gpio->par_fec \|= GPIO_PAR_FEC_7W_FEC \| GPIO_PAR_FEC_MII_FEC;
112	gpio->par_feci2c \|=
113	GPIO_PAR_FECI2C_MDC_EMDC \| GPIO_PAR_FECI2C_MDIO_EMDIO;
114	} else {
115	gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC \| GPIO_PAR_FEC_MII_FEC);
116	gpio->par_feci2c &=
117	~(GPIO_PAR_FECI2C_MDC_EMDC \| GPIO_PAR_FECI2C_MDIO_EMDIO);
118	}
119	return 0;
120	}
121
122	#if defined(CFG_DISCOVER_PHY) \|\| (CONFIG_COMMANDS & CFG_CMD_MII)
123	#include <miiphy.h>
124
125	/* Make MII read/write commands for the FEC. */
126	#define mk_mii_read(ADDR, REG) (0x60020000 \| ((ADDR << 23) \| \
127	(REG & 0x1f) << 18))
128
129	#define mk_mii_write(ADDR, REG, VAL) (0x50020000 \| ((ADDR << 23) \| \
130	(REG & 0x1f) << 18) \| \
131	(VAL & 0xffff))
132
133	/* PHY identification */
134	#define PHY_ID_LXT970 0x78100000 /* LXT970 */
135	#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
136	#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
137	#define PHY_ID_QS6612 0x01814400 /* QS6612 */
138	#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
139	#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
140	#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
141	#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
142	#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
143
144	#define STR_ID_LXT970 "LXT970"
145	#define STR_ID_LXT971 "LXT971"
146	#define STR_ID_82555 "Intel82555"
147	#define STR_ID_QS6612 "QS6612"
148	#define STR_ID_AMD79C784 "AMD79C784"
149	#define STR_ID_LSI80225 "LSI80225"
150	#define STR_ID_LSI80225B "LSI80225/B"
151	#define STR_ID_DP83848VV "N83848"
152	#define STR_ID_DP83849 "N83849"
153
154	/****************************************************************************
155	* mii_init -- Initialize the MII for MII command without ethernet
156	* This function is a subset of eth_init
157	****************************************************************************
158	*/
159	void mii_reset(struct fec_info_s *info)
160	{
161	volatile fec_t fecp = (fec_t ) (info->miibase);
162	int i;
163
164	fecp->ecr = FEC_ECR_RESET;
165	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
166	udelay(1);
167	}
168	if (i == FEC_RESET_DELAY) {
169	printf("FEC_RESET_DELAY timeout\n");
170	}
171	}
172
173	/* send command to phy using mii, wait for result */
174	uint mii_send(uint mii_cmd)
175	{
176	struct fec_info_s *info;
177	struct eth_device *dev;
178	volatile fec_t *ep;
179	uint mii_reply;
180	int j = 0;
181
182	/* retrieve from register structure */
183	dev = eth_get_dev();
184	info = dev->priv;
185
186	ep = (fec_t *) info->miibase;
187
188	ep->mmfr = mii_cmd; /* command to phy */
189
190	/* wait for mii complete */
191	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
192	udelay(1);
193	j++;
194	}
195	if (j >= MCFFEC_TOUT_LOOP) {
196	printf("MII not complete\n");
197	return -1;
198	}
199
200	mii_reply = ep->mmfr; /* result from phy */
201	ep->eir = FEC_EIR_MII; /* clear MII complete */
202	#ifdef ET_DEBUG
203	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
204	__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
205	#endif
206
207	return (mii_reply & 0xffff); /* data read from phy */
208	}
209	#endif /* CFG_DISCOVER_PHY \|\| (CONFIG_COMMANDS & CFG_CMD_MII) */
210
211	#if defined(CFG_DISCOVER_PHY)
212	int mii_discover_phy(struct eth_device *dev)
213	{
214	#define MAX_PHY_PASSES 11
215	struct fec_info_s *info = dev->priv;
216	int phyaddr, pass;
217	uint phyno, phytype;
218
219	if (info->phyname_init)
220	return info->phy_addr;
221
222	phyaddr = -1; /* didn't find a PHY yet */
223	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
224	if (pass > 1) {
225	/* PHY may need more time to recover from reset.
226	* The LXT970 needs 50ms typical, no maximum is
227	* specified, so wait 10ms before try again.
228	* With 11 passes this gives it 100ms to wake up.
229	*/
230	udelay(10000); /* wait 10ms */
231	}
232
233	for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
234
235	phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
236	#ifdef ET_DEBUG
237	printf("PHY type 0x%x pass %d type\n", phytype, pass);
238	#endif
239	if (phytype != 0xffff) {
240	phyaddr = phyno;
241	phytype <<= 16;
242	phytype \|=
243	mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
244
245	switch (phytype & 0xffffffff) {
246	case PHY_ID_DP83848VV:
247	strcpy(info->phy_name,
248	STR_ID_DP83848VV);
249	info->phyname_init = 1;
250	break;
251	default:
252	strcpy(info->phy_name, "unknown");
253	info->phyname_init = 1;
254	break;
255	}
256
257	#ifdef ET_DEBUG
258	printf("PHY @ 0x%x pass %d type ", phyno, pass);
259	switch (phytype & 0xffffffff) {
260	case PHY_ID_DP83848VV:
261	printf(STR_ID_DP83848VV);
262	break;
263	default:
264	printf("0x%08x\n", phytype);
265	break;
266	}
267	#endif
268	}
269	}
270	}
271	if (phyaddr < 0)
272	printf("No PHY device found.\n");
273
274	return phyaddr;
275	}
276	#endif /* CFG_DISCOVER_PHY */
277
278	void mii_init(void)
279	{
280	volatile fec_t *fecp;
281	struct fec_info_s *info;
282	struct eth_device *dev;
283	int miispd = 0, i = 0;
284	u16 autoneg = 0;
285
286	/* retrieve from register structure */
287	dev = eth_get_dev();
288	info = dev->priv;
289
290	fecp = (fec_t *) info->miibase;
291
292	fecpin_setclear(dev, 1);
293
294	mii_reset(info);
295
296	/* We use strictly polling mode only */
297	fecp->eimr = 0;
298
299	/* Clear any pending interrupt */
300	fecp->eir = 0xffffffff;
301
302	/* Set MII speed */
303	miispd = (gd->bus_clk / 1000000) / 5;
304	fecp->mscr = miispd << 1;
305
306	info->phy_addr = mii_discover_phy(dev);
307
308	#define AUTONEGLINK (PHY_BMSR_AUTN_COMP \| PHY_BMSR_LS)
309	while (i < MCFFEC_TOUT_LOOP) {
310	autoneg = 0;
311	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
312	i++;
313
314	if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
315	break;
316
317	udelay(500);
318	}
319	if (i >= MCFFEC_TOUT_LOOP) {
320	printf("Auto Negotiation not complete\n");
321	}
322
323	/* adapt to the half/full speed settings */
324	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
325	info->dup_spd \|= miiphy_speed(dev->name, info->phy_addr);
326	}
327
328	/*****************************************************************************
329	* Read and write a MII PHY register, routines used by MII Utilities
330	*
331	* FIXME: These routines are expected to return 0 on success, but mii_send
332	* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
333	* no PHY connected...
334	* For now always return 0.
335	* FIXME: These routines only work after calling eth_init() at least once!
336	* Otherwise they hang in mii_send() !!! Sorry!
337	*****************************************************************************/
338
339	int mcffec_miiphy_read(char *devname, unsigned char addr,
340	unsigned char reg, unsigned short *value)
341	{
342	short rdreg; /* register working value */
343
344	#ifdef MII_DEBUG
345	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
346	#endif
347	rdreg = mii_send(mk_mii_read(addr, reg));
348
349	*value = rdreg;
350
351	#ifdef MII_DEBUG
352	printf("0x%04x\n", *value);
353	#endif
354
355	return 0;
356	}
357
358	int mcffec_miiphy_write(char *devname, unsigned char addr,
359	unsigned char reg, unsigned short value)
360	{
361	short rdreg; /* register working value */
362
363	#ifdef MII_DEBUG
364	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
365	#endif
366
367	rdreg = mii_send(mk_mii_write(addr, reg, value));
368
369	#ifdef MII_DEBUG
370	printf("0x%04x\n", value);
371	#endif
372
373	return 0;
374	}
375
376	#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */