projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 1a33ce65 TL |
2 | /* |
| 3 | * (C) Copyright 2000-2003 | |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 5 | * | |
| aa0d99fc | 6 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
| 1a33ce65 | 7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 1a33ce65 TL |
8 | */ |
| 9 | ||
| 10 | #include <config.h> | |
| d678a59d | 11 | #include <common.h> |
| 1a33ce65 TL |
12 | #include <asm/io.h> |
| 13 | #include <asm/immap.h> | |
| 14 | ||
| ab77bc54 | 15 | #if defined(CONFIG_CMD_NAND) |
| 1a33ce65 TL |
16 | #include <nand.h> |
| 17 | #include <linux/mtd/mtd.h> | |
| 1cefed1e | 18 | #include <linux/mtd/rawnand.h> |
| 1a33ce65 | 19 | |
| 3ba4c2d6 | 20 | #define SET_CLE 0x10 |
| 3ba4c2d6 | 21 | #define SET_ALE 0x08 |
| 1a33ce65 | 22 | |
| e4f69d1b | 23 | static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) |
| 1a33ce65 | 24 | { |
| 17cb4b8f | 25 | struct nand_chip *this = mtd_to_nand(mtdinfo); |
| 65cc0e2a | 26 | volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; |
| 1a33ce65 | 27 | |
| cfa460ad | 28 | if (ctrl & NAND_CTRL_CHANGE) { |
| e4f69d1b | 29 | ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
| cfa460ad | 30 | |
| e4f69d1b | 31 | IO_ADDR_W &= ~(SET_ALE | SET_CLE); |
| 1a33ce65 | 32 | |
| e4f69d1b | 33 | if (ctrl & NAND_NCE) |
| 9017d932 TL |
34 | *nCE &= 0xFFFB; |
| 35 | else | |
| e4f69d1b | 36 | *nCE |= 0x0004; |
| 9017d932 | 37 | |
| e4f69d1b TL |
38 | if (ctrl & NAND_CLE) |
| 39 | IO_ADDR_W |= SET_CLE; | |
| 40 | if (ctrl & NAND_ALE) | |
| 41 | IO_ADDR_W |= SET_ALE; | |
| 1a33ce65 | 42 | |
| e4f69d1b TL |
43 | this->IO_ADDR_W = (void *)IO_ADDR_W; |
| 44 | } | |
| 1a33ce65 | 45 | |
| e4f69d1b TL |
46 | if (cmd != NAND_CMD_NONE) |
| 47 | writeb(cmd, this->IO_ADDR_W); | |
| 1a33ce65 TL |
48 | } |
| 49 | ||
| 50 | int board_nand_init(struct nand_chip *nand) | |
| 51 | { | |
| aa0d99fc | 52 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
| 1a33ce65 | 53 | |
| e4f69d1b TL |
54 | /* |
| 55 | * set up pin configuration - enabled 2nd output buffer's signals | |
| 56 | * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) | |
| 57 | * to use nCE signal | |
| 58 | */ | |
| aa0d99fc AW |
59 | clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); |
| 60 | setbits_8(&gpio->pddr_timer, 0x08); | |
| 61 | setbits_8(&gpio->ppd_timer, 0x08); | |
| 62 | out_8(&gpio->pclrr_timer, 0); | |
| 63 | out_8(&gpio->podr_timer, 0); | |
| 1a33ce65 | 64 | |
| 9017d932 | 65 | nand->chip_delay = 60; |
| cfa460ad WJ |
66 | nand->ecc.mode = NAND_ECC_SOFT; |
| 67 | nand->cmd_ctrl = nand_hwcontrol; | |
| 1a33ce65 | 68 | |
| 3ba4c2d6 | 69 | return 0; |
| 1a33ce65 TL |
70 | } |
| 71 | #endif |