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1aee1111 TL |
1 | /* |
2 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
3 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <config.h> | |
26 | #include <net.h> | |
27 | ||
28 | #include <asm/immap.h> | |
29 | #include <asm/fec.h> | |
30 | #include <asm/fsl_mcdmafec.h> | |
31 | ||
32 | DECLARE_GLOBAL_DATA_PTR; | |
33 | ||
34 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) | |
35 | #undef MII_DEBUG | |
36 | #undef ET_DEBUG | |
37 | ||
38 | int fecpin_setclear(struct eth_device *dev, int setclear) | |
39 | { | |
40 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; | |
41 | struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; | |
42 | ||
43 | if (setclear) { | |
6d0f6bcf | 44 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) |
1aee1111 TL |
45 | gpio->par_feci2cirq |= 0xF000; |
46 | else | |
47 | gpio->par_feci2cirq |= 0x0FC0; | |
48 | } else { | |
6d0f6bcf | 49 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) |
1aee1111 TL |
50 | gpio->par_feci2cirq &= 0x0FFF; |
51 | else | |
52 | gpio->par_feci2cirq &= 0xF03F; | |
53 | } | |
54 | return 0; | |
55 | } | |
56 | ||
6d0f6bcf | 57 | #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII) |
1aee1111 TL |
58 | #include <miiphy.h> |
59 | ||
60 | /* Make MII read/write commands for the FEC. */ | |
61 | #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) | |
62 | ||
63 | #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) | |
64 | ||
65 | /* PHY identification */ | |
66 | #define PHY_ID_LXT970 0x78100000 /* LXT970 */ | |
67 | #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ | |
68 | #define PHY_ID_82555 0x02a80150 /* Intel 82555 */ | |
69 | #define PHY_ID_QS6612 0x01814400 /* QS6612 */ | |
70 | #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ | |
71 | #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ | |
72 | #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ | |
73 | #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ | |
74 | #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ | |
75 | #define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */ | |
76 | ||
77 | #define STR_ID_LXT970 "LXT970" | |
78 | #define STR_ID_LXT971 "LXT971" | |
79 | #define STR_ID_82555 "Intel82555" | |
80 | #define STR_ID_QS6612 "QS6612" | |
81 | #define STR_ID_AMD79C784 "AMD79C784" | |
82 | #define STR_ID_LSI80225 "LSI80225" | |
83 | #define STR_ID_LSI80225B "LSI80225/B" | |
84 | #define STR_ID_DP83848VV "N83848" | |
85 | #define STR_ID_DP83849 "N83849" | |
86 | #define STR_ID_BCM5222 "BCM5222" | |
87 | ||
88 | /**************************************************************************** | |
89 | * mii_init -- Initialize the MII for MII command without ethernet | |
90 | * This function is a subset of eth_init | |
91 | **************************************************************************** | |
92 | */ | |
93 | void mii_reset(struct fec_info_dma *info) | |
94 | { | |
95 | volatile fecdma_t *fecp = (fecdma_t *) (info->miibase); | |
96 | int i; | |
97 | ||
98 | fecp->ecr = FEC_ECR_RESET; | |
99 | for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { | |
100 | udelay(1); | |
101 | } | |
102 | if (i == FEC_RESET_DELAY) { | |
103 | printf("FEC_RESET_DELAY timeout\n"); | |
104 | } | |
105 | } | |
106 | ||
107 | /* send command to phy using mii, wait for result */ | |
108 | uint mii_send(uint mii_cmd) | |
109 | { | |
110 | struct fec_info_dma *info; | |
111 | struct eth_device *dev; | |
112 | volatile fecdma_t *ep; | |
113 | uint mii_reply; | |
114 | int j = 0; | |
115 | ||
116 | /* retrieve from register structure */ | |
117 | dev = eth_get_dev(); | |
118 | info = dev->priv; | |
119 | ||
120 | ep = (fecdma_t *) info->miibase; | |
121 | ||
122 | ep->mmfr = mii_cmd; /* command to phy */ | |
123 | ||
124 | /* wait for mii complete */ | |
125 | while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { | |
126 | udelay(1); | |
127 | j++; | |
128 | } | |
129 | if (j >= MCFFEC_TOUT_LOOP) { | |
130 | printf("MII not complete\n"); | |
131 | return -1; | |
132 | } | |
133 | ||
134 | mii_reply = ep->mmfr; /* result from phy */ | |
135 | ep->eir = FEC_EIR_MII; /* clear MII complete */ | |
136 | #ifdef ET_DEBUG | |
137 | printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", | |
138 | __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); | |
139 | #endif | |
140 | ||
141 | return (mii_reply & 0xffff); /* data read from phy */ | |
142 | } | |
6d0f6bcf | 143 | #endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */ |
1aee1111 | 144 | |
6d0f6bcf | 145 | #if defined(CONFIG_SYS_DISCOVER_PHY) |
1aee1111 TL |
146 | int mii_discover_phy(struct eth_device *dev) |
147 | { | |
148 | #define MAX_PHY_PASSES 11 | |
149 | struct fec_info_dma *info = dev->priv; | |
150 | int phyaddr, pass, temp; | |
151 | uint phyno, phytype; | |
152 | ||
153 | if (info->phyname_init) { | |
154 | return info->phy_addr; | |
155 | } | |
156 | ||
157 | phyaddr = -1; /* didn't find a PHY yet */ | |
158 | for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { | |
159 | if (pass > 1) { | |
160 | /* PHY may need more time to recover from reset. | |
161 | * The LXT970 needs 50ms typical, no maximum is | |
162 | * specified, so wait 10ms before try again. | |
163 | * With 11 passes this gives it 100ms to wake up. | |
164 | */ | |
165 | udelay(10000); /* wait 10ms */ | |
166 | } | |
167 | ||
168 | temp = 0; | |
169 | if (info->index > 0) { | |
170 | /* Some phy have multiple address, to solve the issue | |
171 | where phyno keeps starting from 0, check the | |
172 | previous phy address if both miibase are the same. */ | |
173 | if (info->miibase == (info->next)->miibase) { | |
174 | temp = (info->next)->phy_addr + 1; | |
175 | } | |
176 | } | |
177 | ||
178 | for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) { | |
179 | ||
180 | phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); | |
181 | #ifdef ET_DEBUG | |
182 | printf("PHY type 0x%x pass %d type\n", phytype, pass); | |
183 | #endif | |
184 | if (phytype != 0xffff) { | |
185 | phyaddr = phyno; | |
186 | phytype <<= 16; | |
187 | phytype |= | |
188 | mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); | |
189 | ||
190 | switch (phytype & 0xffffffff) { | |
191 | case PHY_ID_BCM5222: | |
192 | strcpy(info->phy_name, STR_ID_BCM5222); | |
193 | info->phyname_init = 1; | |
194 | break; | |
195 | default: | |
196 | strcpy(info->phy_name, "unknown"); | |
197 | info->phyname_init = 1; | |
198 | break; | |
199 | } | |
200 | ||
201 | #ifdef ET_DEBUG | |
202 | printf("PHY @ 0x%x pass %d type ", phyno, pass); | |
203 | switch (phytype & 0xffffffff) { | |
204 | case PHY_ID_BCM5222: | |
205 | printf(STR_ID_BCM5222); | |
206 | break; | |
207 | default: | |
208 | printf("0x%08x\n", phytype); | |
209 | break; | |
210 | } | |
211 | #endif | |
212 | } | |
213 | } | |
214 | } | |
215 | if (phyaddr < 0) | |
216 | printf("No PHY device found.\n"); | |
217 | ||
218 | return phyaddr; | |
219 | } | |
6d0f6bcf | 220 | #endif /* CONFIG_SYS_DISCOVER_PHY */ |
1aee1111 TL |
221 | |
222 | void mii_init(void) __attribute__ ((weak, alias("__mii_init"))); | |
223 | ||
224 | void __mii_init(void) | |
225 | { | |
226 | volatile fecdma_t *fecp; | |
227 | struct fec_info_dma *info; | |
228 | struct eth_device *dev; | |
229 | int miispd = 0, i = 0; | |
230 | u16 autoneg = 0; | |
231 | ||
232 | /* retrieve from register structure */ | |
233 | dev = eth_get_dev(); | |
234 | info = dev->priv; | |
235 | ||
236 | fecp = (fecdma_t *) info->miibase; | |
237 | ||
238 | fecpin_setclear(dev, 1); | |
239 | ||
240 | mii_reset(info); | |
241 | ||
242 | /* We use strictly polling mode only */ | |
243 | fecp->eimr = 0; | |
244 | ||
245 | /* Clear any pending interrupt */ | |
246 | fecp->eir = 0xffffffff; | |
247 | ||
248 | /* Set MII speed */ | |
249 | miispd = (gd->bus_clk / 1000000) / 5; | |
250 | fecp->mscr = miispd << 1; | |
251 | ||
252 | info->phy_addr = mii_discover_phy(dev); | |
253 | ||
254 | #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) | |
255 | while (i < MCFFEC_TOUT_LOOP) { | |
256 | autoneg = 0; | |
257 | miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); | |
258 | i++; | |
259 | ||
260 | if ((autoneg & AUTONEGLINK) == AUTONEGLINK) | |
261 | break; | |
262 | ||
263 | udelay(500); | |
264 | } | |
265 | if (i >= MCFFEC_TOUT_LOOP) { | |
266 | printf("Auto Negotiation not complete\n"); | |
267 | } | |
268 | ||
269 | /* adapt to the half/full speed settings */ | |
270 | info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; | |
271 | info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); | |
272 | } | |
273 | ||
274 | /***************************************************************************** | |
275 | * Read and write a MII PHY register, routines used by MII Utilities | |
276 | * | |
277 | * FIXME: These routines are expected to return 0 on success, but mii_send | |
278 | * does _not_ return an error code. Maybe 0xFFFF means error, i.e. | |
279 | * no PHY connected... | |
280 | * For now always return 0. | |
281 | * FIXME: These routines only work after calling eth_init() at least once! | |
282 | * Otherwise they hang in mii_send() !!! Sorry! | |
283 | *****************************************************************************/ | |
284 | ||
285 | int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, | |
286 | unsigned short *value) | |
287 | { | |
288 | short rdreg; /* register working value */ | |
289 | ||
290 | #ifdef MII_DEBUG | |
291 | printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); | |
292 | #endif | |
293 | rdreg = mii_send(mk_mii_read(addr, reg)); | |
294 | ||
295 | *value = rdreg; | |
296 | ||
297 | #ifdef MII_DEBUG | |
298 | printf("0x%04x\n", *value); | |
299 | #endif | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, | |
305 | unsigned short value) | |
306 | { | |
307 | short rdreg; /* register working value */ | |
308 | ||
309 | #ifdef MII_DEBUG | |
310 | printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); | |
311 | #endif | |
312 | ||
313 | rdreg = mii_send(mk_mii_write(addr, reg, value)); | |
314 | ||
315 | #ifdef MII_DEBUG | |
316 | printf("0x%04x\n", value); | |
317 | #endif | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ |