]>
Commit | Line | Data |
---|---|---|
96b8a054 SW |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 | |
3 | * | |
4 | * Author: Scott Wood <scottwood@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
b3458d2c | 26 | #if defined(CONFIG_OF_LIBFDT) |
3fde9e8b KP |
27 | #include <libfdt.h> |
28 | #endif | |
96b8a054 SW |
29 | #include <pci.h> |
30 | #include <mpc83xx.h> | |
89c7784e | 31 | #include <vsc7385.h> |
e4c09508 SW |
32 | #include <ns16550.h> |
33 | #include <nand.h> | |
96b8a054 SW |
34 | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
37 | int board_early_init_f(void) | |
38 | { | |
6d0f6bcf JCPV |
39 | #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC |
40 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
96b8a054 SW |
41 | |
42 | if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) | |
43 | gd->flags |= GD_FLG_SILENT; | |
44 | #endif | |
45 | ||
46 | return 0; | |
47 | } | |
48 | ||
49 | int checkboard(void) | |
50 | { | |
51 | puts("Board: Freescale MPC8313ERDB\n"); | |
52 | return 0; | |
53 | } | |
54 | ||
e4c09508 | 55 | #ifndef CONFIG_NAND_SPL |
96b8a054 SW |
56 | static struct pci_region pci_regions[] = { |
57 | { | |
6d0f6bcf JCPV |
58 | bus_start: CONFIG_SYS_PCI1_MEM_BASE, |
59 | phys_start: CONFIG_SYS_PCI1_MEM_PHYS, | |
60 | size: CONFIG_SYS_PCI1_MEM_SIZE, | |
96b8a054 SW |
61 | flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
62 | }, | |
63 | { | |
6d0f6bcf JCPV |
64 | bus_start: CONFIG_SYS_PCI1_MMIO_BASE, |
65 | phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, | |
66 | size: CONFIG_SYS_PCI1_MMIO_SIZE, | |
96b8a054 SW |
67 | flags: PCI_REGION_MEM |
68 | }, | |
69 | { | |
6d0f6bcf JCPV |
70 | bus_start: CONFIG_SYS_PCI1_IO_BASE, |
71 | phys_start: CONFIG_SYS_PCI1_IO_PHYS, | |
72 | size: CONFIG_SYS_PCI1_IO_SIZE, | |
96b8a054 SW |
73 | flags: PCI_REGION_IO |
74 | } | |
75 | }; | |
76 | ||
77 | void pci_init_board(void) | |
78 | { | |
6d0f6bcf | 79 | volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
96b8a054 SW |
80 | volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
81 | volatile law83xx_t *pci_law = immr->sysconf.pcilaw; | |
82 | struct pci_region *reg[] = { pci_regions }; | |
83 | int warmboot; | |
84 | ||
85 | /* Enable all 3 PCI_CLK_OUTPUTs. */ | |
86 | clk->occr |= 0xe0000000; | |
87 | ||
88 | /* | |
89 | * Configure PCI Local Access Windows | |
90 | */ | |
6d0f6bcf | 91 | pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
96b8a054 SW |
92 | pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; |
93 | ||
6d0f6bcf | 94 | pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
96b8a054 SW |
95 | pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
96 | ||
97 | warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; | |
6d0f6bcf | 98 | #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC |
96b8a054 SW |
99 | warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; |
100 | #endif | |
101 | ||
102 | mpc83xx_pci_init(1, reg, warmboot); | |
103 | } | |
104 | ||
89c7784e TT |
105 | /* |
106 | * Miscellaneous late-boot configurations | |
107 | * | |
108 | * If a VSC7385 microcode image is present, then upload it. | |
109 | */ | |
110 | int misc_init_r(void) | |
111 | { | |
112 | int rc = 0; | |
113 | ||
114 | #ifdef CONFIG_VSC7385_IMAGE | |
115 | if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, | |
116 | CONFIG_VSC7385_IMAGE_SIZE)) { | |
117 | puts("Failure uploading VSC7385 microcode.\n"); | |
118 | rc = 1; | |
119 | } | |
120 | #endif | |
121 | ||
122 | return rc; | |
123 | } | |
124 | ||
3fde9e8b | 125 | #if defined(CONFIG_OF_BOARD_SETUP) |
96b8a054 SW |
126 | void ft_board_setup(void *blob, bd_t *bd) |
127 | { | |
3fde9e8b KP |
128 | ft_cpu_setup(blob, bd); |
129 | #ifdef CONFIG_PCI | |
130 | ft_pci_setup(blob, bd); | |
131 | #endif | |
96b8a054 SW |
132 | } |
133 | #endif | |
e4c09508 SW |
134 | #else /* CONFIG_NAND_SPL */ |
135 | void board_init_f(ulong bootflag) | |
136 | { | |
137 | board_early_init_f(); | |
6d0f6bcf JCPV |
138 | NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), |
139 | CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); | |
e4c09508 SW |
140 | puts("NAND boot... "); |
141 | init_timebase(); | |
142 | initdram(0); | |
6d0f6bcf JCPV |
143 | relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, |
144 | CONFIG_SYS_NAND_U_BOOT_RELOC); | |
e4c09508 SW |
145 | } |
146 | ||
147 | void board_init_r(gd_t *gd, ulong dest_addr) | |
148 | { | |
149 | nand_boot(); | |
150 | } | |
151 | ||
152 | void putc(char c) | |
153 | { | |
154 | if (gd->flags & GD_FLG_SILENT) | |
155 | return; | |
156 | ||
157 | if (c == '\n') | |
6d0f6bcf | 158 | NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); |
e4c09508 | 159 | |
6d0f6bcf | 160 | NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); |
e4c09508 SW |
161 | } |
162 | #endif |