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96b8a054 SW |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 | |
3 | * | |
4 | * Authors: Nick.Spence@freescale.com | |
5 | * Wilson.Lo@freescale.com | |
6 | * scottwood@freescale.com | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <mpc83xx.h> | |
29 | #include <spd_sdram.h> | |
30 | ||
31 | #include <asm/bitops.h> | |
32 | #include <asm/io.h> | |
33 | ||
34 | #include <asm/processor.h> | |
35 | ||
36 | #ifndef CFG_8313ERDB_BROKEN_PMC | |
37 | static void resume_from_sleep(void) | |
38 | { | |
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | u32 magic = *(u32 *)0; | |
41 | ||
42 | typedef void (*func_t)(void); | |
43 | func_t resume = *(func_t *)4; | |
44 | ||
45 | if (magic == 0xf5153ae5) | |
46 | resume(); | |
47 | ||
48 | gd->flags &= ~GD_FLG_SILENT; | |
49 | puts("\nResume from sleep failed: bad magic word\n"); | |
50 | } | |
51 | #endif | |
52 | ||
53 | /* Fixed sdram init -- doesn't use serial presence detect. | |
54 | * | |
55 | * This is useful for faster booting in configs where the RAM is unlikely | |
56 | * to be changed, or for things like NAND booting where space is tight. | |
57 | */ | |
58 | static long fixed_sdram(void) | |
59 | { | |
60 | volatile immap_t *im = (volatile immap_t *)CFG_IMMR; | |
61 | u32 msize = CFG_DDR_SIZE * 1024 * 1024; | |
62 | u32 msize_log2 = __ilog2(msize); | |
63 | ||
64 | im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; | |
65 | im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); | |
66 | im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; | |
67 | ||
68 | /* | |
69 | * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], | |
70 | * or the DDR2 controller may fail to initialize correctly. | |
71 | */ | |
72 | udelay(50000); | |
73 | ||
74 | im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; | |
75 | im->ddr.cs_config[0] = CFG_DDR_CONFIG; | |
76 | ||
77 | /* Currently we use only one CS, so disable the other bank. */ | |
78 | im->ddr.cs_config[1] = 0; | |
79 | ||
80 | im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; | |
81 | im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; | |
82 | im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; | |
83 | im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; | |
84 | im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; | |
85 | ||
86 | #ifndef CFG_8313ERDB_BROKEN_PMC | |
87 | if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) | |
88 | im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; | |
89 | else | |
90 | #endif | |
91 | im->ddr.sdram_cfg = CFG_SDRAM_CFG; | |
92 | ||
93 | im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; | |
94 | im->ddr.sdram_mode = CFG_DDR_MODE; | |
95 | im->ddr.sdram_mode2 = CFG_DDR_MODE_2; | |
96 | ||
97 | im->ddr.sdram_interval = CFG_DDR_INTERVAL; | |
98 | sync(); | |
99 | ||
100 | /* enable DDR controller */ | |
101 | im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; | |
102 | ||
103 | return msize; | |
104 | } | |
105 | ||
106 | long int initdram(int board_type) | |
107 | { | |
108 | volatile immap_t *im = (volatile immap_t *)CFG_IMMR; | |
109 | volatile lbus83xx_t *lbc = &im->lbus; | |
110 | u32 msize; | |
111 | ||
112 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) | |
113 | return -1; | |
114 | ||
96b8a054 SW |
115 | /* DDR SDRAM - Main SODIMM */ |
116 | msize = fixed_sdram(); | |
117 | ||
118 | /* Local Bus setup lbcr and mrtpr */ | |
119 | lbc->lbcr = CFG_LBC_LBCR; | |
120 | lbc->mrtpr = CFG_LBC_MRTPR; | |
121 | sync(); | |
122 | ||
123 | #ifndef CFG_8313ERDB_BROKEN_PMC | |
124 | if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) | |
125 | resume_from_sleep(); | |
126 | #endif | |
127 | ||
96b8a054 SW |
128 | /* return total bus SDRAM size(bytes) -- DDR */ |
129 | return msize; | |
130 | } |