[people/ms/u-boot.git] / board / freescale / mpc8323erdb / mpc8323erdb.c

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * Michael Barkowski <michael.barkowski@freescale.com>
 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <command.h>
#include <libfdt.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#include <asm/mmu.h>

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* UCC3 */
	{1,  0, 1, 0, 1}, /* TxD0 */
	{1,  1, 1, 0, 1}, /* TxD1 */
	{1,  2, 1, 0, 1}, /* TxD2 */
	{1,  3, 1, 0, 1}, /* TxD3 */
	{1,  9, 1, 0, 1}, /* TxER */
	{1, 12, 1, 0, 1}, /* TxEN */
	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */

	{1,  4, 2, 0, 1}, /* RxD0 */
	{1,  5, 2, 0, 1}, /* RxD1 */
	{1,  6, 2, 0, 1}, /* RxD2 */
	{1,  7, 2, 0, 1}, /* RxD3 */
	{1,  8, 2, 0, 1}, /* RxER */
	{1, 10, 2, 0, 1}, /* RxDV */
	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
	{1, 11, 2, 0, 1}, /* COL */
	{1, 13, 2, 0, 1}, /* CRS */

	/* UCC2 */
	{0, 18, 1, 0, 1}, /* TxD0 */
	{0, 19, 1, 0, 1}, /* TxD1 */
	{0, 20, 1, 0, 1}, /* TxD2 */
	{0, 21, 1, 0, 1}, /* TxD3 */
	{0, 27, 1, 0, 1}, /* TxER */
	{0, 30, 1, 0, 1}, /* TxEN */
	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */

	{0, 22, 2, 0, 1}, /* RxD0 */
	{0, 23, 2, 0, 1}, /* RxD1 */
	{0, 24, 2, 0, 1}, /* RxD2 */
	{0, 25, 2, 0, 1}, /* RxD3 */
	{0, 26, 1, 0, 1}, /* RxER */
	{0, 28, 2, 0, 1}, /* Rx_DV */
	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
	{0, 29, 2, 0, 1}, /* COL */
	{0, 31, 2, 0, 1}, /* CRS */

	{3,  4, 3, 0, 2}, /* MDIO */
	{3,  5, 1, 0, 2}, /* MDC */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

int board_early_init_f(void)
{
	return 0;
}

int fixed_sdram(void);

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;

	msize = fixed_sdram();

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CONFIG_SYS_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].ar =
	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	__asm__ __volatile__ ("sync");
	udelay(200);

	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	__asm__ __volatile__ ("sync");
	return msize;
}

int checkboard(void)
{
	puts("Board: Freescale MPC8323ERDB\n");
	return 0;
}

static struct pci_region pci_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
		size: CONFIG_SYS_PCI1_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
		size: CONFIG_SYS_PCI1_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
	{
		bus_start: CONFIG_SYS_PCI1_IO_BASE,
		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
		size: CONFIG_SYS_PCI1_IO_SIZE,
		flags: PCI_REGION_IO
	}
};

void pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	struct pci_region *reg[] = { pci_regions };

	/* Enable all 3 PCI_CLK_OUTPUTs. */
	clk->occr |= 0xe0000000;

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;

	mpc83xx_pci_init(1, reg, 0);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
}
#endif

#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
int mac_read_from_eeprom(void)
{
	uchar buf[28];
	char str[18];
	int i = 0;
	unsigned int crc = 0;
	unsigned char enetvar[32];

	/* Read MAC addresses from EEPROM */
	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
		       CONFIG_SYS_I2C_EEPROM_ADDR);
	} else {
		if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
			printf("Reading MAC from EEPROM\n");
			for (i = 0; i < 4; i++) {
				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
					sprintf(str,
						"%02X:%02X:%02X:%02X:%02X:%02X",
						buf[i * 6], buf[i * 6 + 1],
						buf[i * 6 + 2], buf[i * 6 + 3],
						buf[i * 6 + 4], buf[i * 6 + 5]);
					sprintf((char *)enetvar,
						i ? "eth%daddr" : "ethaddr", i);
					setenv((char *)enetvar, str);
				}
			}
		}
	}
	return 0;
}
#endif				/* CONFIG_I2C_MAC_OFFSET */
Commit	Line	Data
1c274c4e KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* Michael Barkowski <michael.barkowski@freescale.com>
	5	* Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published
	9	* by the Free Software Foundation.
	10	*/
	11
	12	#include <common.h>
	13	#include <ioports.h>
	14	#include <mpc83xx.h>
	15	#include <i2c.h>
1c274c4e KP	16	#include <miiphy.h>
	17	#include <command.h>
	18	#include <libfdt.h>
1c274c4e KP	19	#if defined(CONFIG_PCI)
	20	#include <pci.h>
	21	#endif
1c274c4e	22	#include <asm/mmu.h>
1c274c4e KP	23
	24	const qe_iop_conf_t qe_iop_conf_tab[] = {
	25	/* UCC3 */
	26	{1, 0, 1, 0, 1}, /* TxD0 */
	27	{1, 1, 1, 0, 1}, /* TxD1 */
	28	{1, 2, 1, 0, 1}, /* TxD2 */
	29	{1, 3, 1, 0, 1}, /* TxD3 */
	30	{1, 9, 1, 0, 1}, /* TxER */
	31	{1, 12, 1, 0, 1}, /* TxEN */
	32	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
	33
	34	{1, 4, 2, 0, 1}, /* RxD0 */
	35	{1, 5, 2, 0, 1}, /* RxD1 */
	36	{1, 6, 2, 0, 1}, /* RxD2 */
	37	{1, 7, 2, 0, 1}, /* RxD3 */
	38	{1, 8, 2, 0, 1}, /* RxER */
	39	{1, 10, 2, 0, 1}, /* RxDV */
	40	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
	41	{1, 11, 2, 0, 1}, /* COL */
	42	{1, 13, 2, 0, 1}, /* CRS */
	43
	44	/* UCC2 */
	45	{0, 18, 1, 0, 1}, /* TxD0 */
	46	{0, 19, 1, 0, 1}, /* TxD1 */
	47	{0, 20, 1, 0, 1}, /* TxD2 */
	48	{0, 21, 1, 0, 1}, /* TxD3 */
	49	{0, 27, 1, 0, 1}, /* TxER */
	50	{0, 30, 1, 0, 1}, /* TxEN */
	51	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
	52
	53	{0, 22, 2, 0, 1}, /* RxD0 */
	54	{0, 23, 2, 0, 1}, /* RxD1 */
	55	{0, 24, 2, 0, 1}, /* RxD2 */
	56	{0, 25, 2, 0, 1}, /* RxD3 */
	57	{0, 26, 1, 0, 1}, /* RxER */
	58	{0, 28, 2, 0, 1}, /* Rx_DV */
	59	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
	60	{0, 29, 2, 0, 1}, /* COL */
	61	{0, 31, 2, 0, 1}, /* CRS */
	62
	63	{3, 4, 3, 0, 2}, /* MDIO */
	64	{3, 5, 1, 0, 2}, /* MDC */
	65
	66	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	67	};
	68
	69	int board_early_init_f(void)
	70	{
	71	return 0;
	72	}
	73
	74	int fixed_sdram(void);
	75
9973e3c6	76	phys_size_t initdram(int board_type)
1c274c4e	77	{
6d0f6bcf	78	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
1c274c4e KP	79	u32 msize = 0;
	80
	81	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	82	return -1;
	83
	84	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	85	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
1c274c4e KP	86
	87	msize = fixed_sdram();
	88
1c274c4e KP	89	/* return total bus SDRAM size(bytes) -- DDR */
	90	return (msize * 1024 * 1024);
	91	}
	92
	93	/*************************************************************************
	94	* fixed sdram init -- doesn't use serial presence detect.
	95	************************************************************************/
	96	int fixed_sdram(void)
	97	{
6d0f6bcf	98	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
1c274c4e KP	99	u32 msize = 0;
	100	u32 ddr_size;
	101	u32 ddr_size_log2;
	102
6d0f6bcf	103	msize = CONFIG_SYS_DDR_SIZE;
1c274c4e KP	104	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	105	(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
	106	if (ddr_size & 1) {
	107	return -1;
	108	}
	109	}
	110	im->sysconf.ddrlaw[0].ar =
	111	LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
6d0f6bcf JCPV	112	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
	113	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	114	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	115	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	116	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	117	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	118	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	119	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	120	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	121	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	122	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	123	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
1c274c4e KP	124	__asm__ __volatile__ ("sync");
	125	udelay(200);
	126
	127	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	128	__asm__ __volatile__ ("sync");
	129	return msize;
	130	}
	131
	132	int checkboard(void)
	133	{
	134	puts("Board: Freescale MPC8323ERDB\n");
	135	return 0;
	136	}
	137
	138	static struct pci_region pci_regions[] = {
	139	{
6d0f6bcf JCPV	140	bus_start: CONFIG_SYS_PCI1_MEM_BASE,
	141	phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
	142	size: CONFIG_SYS_PCI1_MEM_SIZE,
1c274c4e KP	143	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	144	},
	145	{
6d0f6bcf JCPV	146	bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
	147	phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
	148	size: CONFIG_SYS_PCI1_MMIO_SIZE,
1c274c4e KP	149	flags: PCI_REGION_MEM
	150	},
	151	{
6d0f6bcf JCPV	152	bus_start: CONFIG_SYS_PCI1_IO_BASE,
	153	phys_start: CONFIG_SYS_PCI1_IO_PHYS,
	154	size: CONFIG_SYS_PCI1_IO_SIZE,
1c274c4e KP	155	flags: PCI_REGION_IO
	156	}
	157	};
	158
	159	void pci_init_board(void)
	160	{
6d0f6bcf	161	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
1c274c4e KP	162	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
	163	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	164	struct pci_region *reg[] = { pci_regions };
	165
	166	/* Enable all 3 PCI_CLK_OUTPUTs. */
	167	clk->occr \|= 0xe0000000;
	168
	169	/* Configure PCI Local Access Windows */
6d0f6bcf	170	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
1c274c4e KP	171	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
1c274c4e KP	172
6d0f6bcf	173	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
1c274c4e KP	174	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
	175
	176	mpc83xx_pci_init(1, reg, 0);
	177	}
	178
	179	#if defined(CONFIG_OF_BOARD_SETUP)
3fde9e8b	180	void ft_board_setup(void blob, bd_t bd)
1c274c4e	181	{
1c274c4e	182	ft_cpu_setup(blob, bd);
1c274c4e KP	183	#ifdef CONFIG_PCI
	184	ft_pci_setup(blob, bd);
	185	#endif
	186	}
3fde9e8b	187	#endif
5b2793a3	188
6d0f6bcf	189	#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
5b2793a3 MB	190	int mac_read_from_eeprom(void)
	191	{
	192	uchar buf[28];
	193	char str[18];
	194	int i = 0;
	195	unsigned int crc = 0;
	196	unsigned char enetvar[32];
	197
	198	/* Read MAC addresses from EEPROM */
6d0f6bcf	199	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
5b2793a3	200	printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
6d0f6bcf	201	CONFIG_SYS_I2C_EEPROM_ADDR);
5b2793a3 MB	202	} else {
	203	if (crc32(crc, buf, 24) == (unsigned int )&buf[24]) {
	204	printf("Reading MAC from EEPROM\n");
	205	for (i = 0; i < 4; i++) {
	206	if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
	207	sprintf(str,
	208	"%02X:%02X:%02X:%02X:%02X:%02X",
	209	buf[i * 6], buf[i * 6 + 1],
	210	buf[i * 6 + 2], buf[i * 6 + 3],
	211	buf[i * 6 + 4], buf[i * 6 + 5]);
	212	sprintf((char *)enetvar,
	213	i ? "eth%daddr" : "ethaddr", i);
	214	setenv((char *)enetvar, str);
	215	}
	216	}
	217	}
	218	}
	219	return 0;
	220	}
	221	#endif /* CONFIG_I2C_MAC_OFFSET */