]>
Commit | Line | Data |
---|---|---|
24c3aca3 DL |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <common.h> | |
16 | #include <ioports.h> | |
17 | #include <mpc83xx.h> | |
18 | #include <i2c.h> | |
24c3aca3 DL |
19 | #include <miiphy.h> |
20 | #include <command.h> | |
21 | #if defined(CONFIG_PCI) | |
22 | #include <pci.h> | |
23 | #endif | |
24c3aca3 | 24 | #include <asm/mmu.h> |
b3458d2c | 25 | #if defined(CONFIG_OF_LIBFDT) |
3fde9e8b | 26 | #include <libfdt.h> |
24c3aca3 | 27 | #endif |
14778585 | 28 | #if defined(CONFIG_PQ_MDS_PIB) |
e58fe957 | 29 | #include "../common/pq-mds-pib.h" |
14778585 | 30 | #endif |
24c3aca3 DL |
31 | |
32 | const qe_iop_conf_t qe_iop_conf_tab[] = { | |
33 | /* ETH3 */ | |
34 | {1, 0, 1, 0, 1}, /* TxD0 */ | |
35 | {1, 1, 1, 0, 1}, /* TxD1 */ | |
36 | {1, 2, 1, 0, 1}, /* TxD2 */ | |
37 | {1, 3, 1, 0, 1}, /* TxD3 */ | |
38 | {1, 9, 1, 0, 1}, /* TxER */ | |
39 | {1, 12, 1, 0, 1}, /* TxEN */ | |
40 | {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ | |
41 | ||
42 | {1, 4, 2, 0, 1}, /* RxD0 */ | |
43 | {1, 5, 2, 0, 1}, /* RxD1 */ | |
44 | {1, 6, 2, 0, 1}, /* RxD2 */ | |
45 | {1, 7, 2, 0, 1}, /* RxD3 */ | |
46 | {1, 8, 2, 0, 1}, /* RxER */ | |
47 | {1, 10, 2, 0, 1}, /* RxDV */ | |
48 | {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ | |
49 | {1, 11, 2, 0, 1}, /* COL */ | |
50 | {1, 13, 2, 0, 1}, /* CRS */ | |
51 | ||
52 | /* ETH4 */ | |
53 | {1, 18, 1, 0, 1}, /* TxD0 */ | |
54 | {1, 19, 1, 0, 1}, /* TxD1 */ | |
55 | {1, 20, 1, 0, 1}, /* TxD2 */ | |
56 | {1, 21, 1, 0, 1}, /* TxD3 */ | |
57 | {1, 27, 1, 0, 1}, /* TxER */ | |
58 | {1, 30, 1, 0, 1}, /* TxEN */ | |
59 | {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ | |
60 | ||
61 | {1, 22, 2, 0, 1}, /* RxD0 */ | |
62 | {1, 23, 2, 0, 1}, /* RxD1 */ | |
63 | {1, 24, 2, 0, 1}, /* RxD2 */ | |
64 | {1, 25, 2, 0, 1}, /* RxD3 */ | |
65 | {1, 26, 1, 0, 1}, /* RxER */ | |
66 | {1, 28, 2, 0, 1}, /* Rx_DV */ | |
67 | {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ | |
68 | {1, 29, 2, 0, 1}, /* COL */ | |
69 | {1, 31, 2, 0, 1}, /* CRS */ | |
70 | ||
71 | {3, 4, 3, 0, 2}, /* MDIO */ | |
72 | {3, 5, 1, 0, 2}, /* MDC */ | |
73 | ||
74 | {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ | |
75 | }; | |
76 | ||
77 | int board_early_init_f(void) | |
78 | { | |
6d0f6bcf | 79 | volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR; |
24c3aca3 DL |
80 | |
81 | /* Enable flash write */ | |
82 | bcsr[9] &= ~0x08; | |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
14778585 TL |
87 | int board_early_init_r(void) |
88 | { | |
89 | #ifdef CONFIG_PQ_MDS_PIB | |
90 | pib_init(); | |
91 | #endif | |
92 | return 0; | |
93 | } | |
94 | ||
24c3aca3 DL |
95 | int fixed_sdram(void); |
96 | ||
9973e3c6 | 97 | phys_size_t initdram(int board_type) |
24c3aca3 | 98 | { |
6d0f6bcf | 99 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
24c3aca3 DL |
100 | u32 msize = 0; |
101 | ||
102 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) | |
103 | return -1; | |
104 | ||
105 | /* DDR SDRAM - Main SODIMM */ | |
6d0f6bcf | 106 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
24c3aca3 DL |
107 | |
108 | msize = fixed_sdram(); | |
109 | ||
24c3aca3 DL |
110 | /* return total bus SDRAM size(bytes) -- DDR */ |
111 | return (msize * 1024 * 1024); | |
112 | } | |
113 | ||
114 | /************************************************************************* | |
115 | * fixed sdram init -- doesn't use serial presence detect. | |
116 | ************************************************************************/ | |
117 | int fixed_sdram(void) | |
118 | { | |
6d0f6bcf | 119 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
24c3aca3 DL |
120 | u32 msize = 0; |
121 | u32 ddr_size; | |
122 | u32 ddr_size_log2; | |
123 | ||
6d0f6bcf | 124 | msize = CONFIG_SYS_DDR_SIZE; |
24c3aca3 DL |
125 | for (ddr_size = msize << 20, ddr_size_log2 = 0; |
126 | (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { | |
127 | if (ddr_size & 1) { | |
128 | return -1; | |
129 | } | |
130 | } | |
131 | im->sysconf.ddrlaw[0].ar = | |
132 | LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); | |
6d0f6bcf | 133 | #if (CONFIG_SYS_DDR_SIZE != 128) |
24c3aca3 DL |
134 | #warning Currenly any ddr size other than 128 is not supported |
135 | #endif | |
6d0f6bcf JCPV |
136 | im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; |
137 | im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; | |
138 | im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; | |
139 | im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; | |
140 | im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; | |
141 | im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; | |
142 | im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; | |
143 | im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; | |
144 | im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; | |
145 | im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; | |
146 | im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; | |
147 | im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; | |
24c3aca3 DL |
148 | __asm__ __volatile__ ("sync"); |
149 | udelay(200); | |
150 | ||
151 | im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; | |
152 | __asm__ __volatile__ ("sync"); | |
153 | return msize; | |
154 | } | |
155 | ||
156 | int checkboard(void) | |
157 | { | |
158 | puts("Board: Freescale MPC832XEMDS\n"); | |
159 | return 0; | |
160 | } | |
161 | ||
3fde9e8b KP |
162 | #if defined(CONFIG_OF_BOARD_SETUP) |
163 | void ft_board_setup(void *blob, bd_t *bd) | |
24c3aca3 | 164 | { |
3fde9e8b KP |
165 | ft_cpu_setup(blob, bd); |
166 | #ifdef CONFIG_PCI | |
167 | ft_pci_setup(blob, bd); | |
168 | #endif | |
24c3aca3 DL |
169 | } |
170 | #endif |