[people/ms/u-boot.git] / board / freescale / mpc8349emds / mpc8349emds.c

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
#include <spd_sdram.h>

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

int fixed_sdram(void);
void sdram_init(void);

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
void ddr_enable_ecc(unsigned int dram_size);
#endif

int board_early_init_f (void)
{
	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;

	/* Enable flash write */
	bcsr[1] &= ~0x01;

#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
	/* Use USB PHY on SYS board */
	bcsr[5] |= 0x02;
#endif

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

phys_size_t initdram (int board_type)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CONFIG_SYS_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1);
	     ddr_size = ddr_size>>1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);

#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
	im->ddr.csbnds[2].csbnds = 0x0000000f;
	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;

	/* currently we use only one CS, so disable the other banks */
	im->ddr.cs_config[0] = 0;
	im->ddr.cs_config[1] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
#if defined (CONFIG_DDR_32BIT)
	/* for 32-bit mode burst length is 8 */
	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;

	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
	udelay(200);

	/* enable DDR controller */
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	return msize;
}
#endif/*!CONFIG_SYS_SPD_EEPROM*/


int checkboard (void)
{
	/*
	 * Warning: do not read the BCSR registers here
	 *
	 * There is a timing bug in the 8349E and 8349EA BCSR code
	 * version 1.2 (read from BCSR 11) that will cause the CFI
	 * flash initialization code to overwrite BCSR 0, disabling
	 * the serial ports and gigabit ethernet
	 */

	puts("Board: Freescale MPC8349EMDS\n");
	return 0;
}

/*
 * if MPC8349EMDS is soldered with SDRAM
 */
#if defined(CONFIG_SYS_BR2_PRELIM)  \
	&& defined(CONFIG_SYS_OR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile lbus83xx_t *lbc= &immap->lbus;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/* setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733; mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
}
#endif

/*
 * The following are used to control the SPI chip selects for the SPI command.
 */
#ifdef CONFIG_MPC8XXX_SPI

#define SPI_CS_MASK	0x80000000

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];

	iopd->dat &= ~SPI_CS_MASK;
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];

	iopd->dat |=  SPI_CS_MASK;
}
#endif /* CONFIG_HARD_SPI */

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
}
#endif
Commit	Line	Data
991425fe MB	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#include <common.h>
	26	#include <ioports.h>
	27	#include <mpc83xx.h>
	28	#include <asm/mpc8349_pci.h>
	29	#include <i2c.h>
80ddd226	30	#include <spi.h>
991425fe	31	#include <miiphy.h>
991425fe	32	#include <spd_sdram.h>
a30a549a	33
b3458d2c	34	#if defined(CONFIG_OF_LIBFDT)
3fde9e8b	35	#include <libfdt.h>
bf0b542d KP	36	#endif
bf0b542d KP	37
991425fe MB	38	int fixed_sdram(void);
	39	void sdram_init(void);
	40
	41	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
	42	void ddr_enable_ecc(unsigned int dram_size);
	43	#endif
	44
	45	int board_early_init_f (void)
	46	{
6d0f6bcf	47	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
991425fe MB	48
	49	/* Enable flash write */
	50	bcsr[1] &= ~0x01;
	51
6d0f6bcf	52	#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
8fe9bf61 KG	53	/* Use USB PHY on SYS board */
	54	bcsr[5] \|= 0x02;
	55	#endif
	56
991425fe MB	57	return 0;
	58	}
	59
	60	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	61
9973e3c6	62	phys_size_t initdram (int board_type)
991425fe	63	{
6d0f6bcf	64	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
991425fe MB	65	u32 msize = 0;
	66
	67	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
	68	return -1;
	69
	70	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	71	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
991425fe	72	#if defined(CONFIG_SPD_EEPROM)
dc9e499c	73	msize = spd_sdram();
991425fe MB	74	#else
	75	msize = fixed_sdram();
	76	#endif
	77	/*
	78	* Initialize SDRAM if it is on local bus.
	79	*/
	80	sdram_init();
	81
	82	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	83	/*
	84	* Initialize and enable DDR ECC.
	85	*/
	86	ddr_enable_ecc(msize * 1024 * 1024);
	87	#endif
bbea46f7	88
991425fe MB	89	/* return total bus SDRAM size(bytes) -- DDR */
	90	return (msize * 1024 * 1024);
	91	}
	92
	93	#if !defined(CONFIG_SPD_EEPROM)
	94	/*************************************************************************
	95	* fixed sdram init -- doesn't use serial presence detect.
	96	************************************************************************/
	97	int fixed_sdram(void)
	98	{
6d0f6bcf	99	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
991425fe MB	100	u32 msize = 0;
	101	u32 ddr_size;
	102	u32 ddr_size_log2;
	103
6d0f6bcf	104	msize = CONFIG_SYS_DDR_SIZE;
991425fe MB	105	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	106	(ddr_size > 1);
	107	ddr_size = ddr_size>>1, ddr_size_log2++) {
	108	if (ddr_size & 1) {
	109	return -1;
	110	}
	111	}
6d0f6bcf	112	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
991425fe	113	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
dc9e499c	114
6d0f6bcf	115	#if (CONFIG_SYS_DDR_SIZE != 256)
991425fe MB	116	#warning Currenly any ddr size other than 256 is not supported
991425fe MB	117	#endif
d61853cf	118	#ifdef CONFIG_DDR_II
6d0f6bcf JCPV	119	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
	120	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
	121	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	122	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	123	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	124	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	125	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	126	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	127	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	128	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	129	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	130	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
d61853cf	131	#else
dc9e499c	132	im->ddr.csbnds[2].csbnds = 0x0000000f;
6d0f6bcf	133	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
dc9e499c	134
cf48eb9a	135	/* currently we use only one CS, so disable the other banks */
dc9e499c RJ	136	im->ddr.cs_config[0] = 0;
	137	im->ddr.cs_config[1] = 0;
	138	im->ddr.cs_config[3] = 0;
	139
6d0f6bcf JCPV	140	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
6d0f6bcf JCPV	141	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
cf48eb9a	142
991425fe MB	143	im->ddr.sdram_cfg =
	144	SDRAM_CFG_SREN
	145	#if defined(CONFIG_DDR_2T_TIMING)
	146	\| SDRAM_CFG_2T_EN
	147	#endif
	148	\| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
dc9e499c RJ	149	#if defined (CONFIG_DDR_32BIT)
	150	/* for 32-bit mode burst length is 8 */
	151	im->ddr.sdram_cfg \|= (SDRAM_CFG_32_BE \| SDRAM_CFG_8_BE);
	152	#endif
6d0f6bcf	153	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
991425fe	154
6d0f6bcf	155	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
d61853cf	156	#endif
991425fe MB	157	udelay(200);
991425fe MB	158
dc9e499c	159	/* enable DDR controller */
991425fe	160	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
991425fe MB	161	return msize;
991425fe MB	162	}
6d0f6bcf	163	#endif/!CONFIG_SYS_SPD_EEPROM/
991425fe MB	164
	165
	166	int checkboard (void)
	167	{
447ad576 IS	168	/*
	169	* Warning: do not read the BCSR registers here
	170	*
	171	* There is a timing bug in the 8349E and 8349EA BCSR code
	172	* version 1.2 (read from BCSR 11) that will cause the CFI
	173	* flash initialization code to overwrite BCSR 0, disabling
	174	* the serial ports and gigabit ethernet
	175	*/
	176
991425fe MB	177	puts("Board: Freescale MPC8349EMDS\n");
	178	return 0;
	179	}
	180
991425fe MB	181	/*
	182	* if MPC8349EMDS is soldered with SDRAM
	183	*/
6d0f6bcf JCPV	184	#if defined(CONFIG_SYS_BR2_PRELIM) \
	185	&& defined(CONFIG_SYS_OR2_PRELIM) \
	186	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	187	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
991425fe MB	188	/*
	189	* Initialize SDRAM memory on the Local Bus.
	190	*/
	191
	192	void sdram_init(void)
	193	{
6d0f6bcf	194	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f6eda7f8	195	volatile lbus83xx_t *lbc= &immap->lbus;
6d0f6bcf	196	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
991425fe	197
991425fe MB	198	/*
	199	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	200	*/
	201
	202	/* setup mtrpt, lsrt and lbcr for LB bus */
6d0f6bcf JCPV	203	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	204	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	205	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
991425fe MB	206	asm("sync");
	207
	208	/*
	209	* Configure the SDRAM controller Machine Mode Register.
	210	*/
6d0f6bcf	211	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
991425fe	212
6d0f6bcf	213	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
991425fe MB	214	asm("sync");
	215	*sdram_addr = 0xff;
	216	udelay(100);
	217
6d0f6bcf	218	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
991425fe MB	219	asm("sync");
	220	/1 times/
	221	*sdram_addr = 0xff;
	222	udelay(100);
	223	/2 times/
	224	*sdram_addr = 0xff;
	225	udelay(100);
	226	/3 times/
	227	*sdram_addr = 0xff;
	228	udelay(100);
	229	/4 times/
	230	*sdram_addr = 0xff;
	231	udelay(100);
	232	/5 times/
	233	*sdram_addr = 0xff;
	234	udelay(100);
	235	/6 times/
	236	*sdram_addr = 0xff;
	237	udelay(100);
	238	/7 times/
	239	*sdram_addr = 0xff;
	240	udelay(100);
	241	/8 times/
	242	*sdram_addr = 0xff;
	243	udelay(100);
	244
	245	/* 0x58636733; mode register write operation */
6d0f6bcf	246	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
991425fe MB	247	asm("sync");
	248	*sdram_addr = 0xff;
	249	udelay(100);
	250
6d0f6bcf	251	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
991425fe MB	252	asm("sync");
	253	*sdram_addr = 0xff;
	254	udelay(100);
	255	}
	256	#else
	257	void sdram_init(void)
	258	{
991425fe MB	259	}
991425fe MB	260	#endif
d326f4a2	261
80ddd226 BW	262	/*
	263	* The following are used to control the SPI chip selects for the SPI command.
	264	*/
f8cc312b	265	#ifdef CONFIG_MPC8XXX_SPI
80ddd226 BW	266
	267	#define SPI_CS_MASK 0x80000000
	268
d255bb0e HS	269	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	270	{
	271	return bus == 0 && cs == 0;
	272	}
	273
	274	void spi_cs_activate(struct spi_slave *slave)
80ddd226	275	{
6d0f6bcf	276	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
80ddd226	277
d255bb0e	278	iopd->dat &= ~SPI_CS_MASK;
80ddd226 BW	279	}
80ddd226 BW	280
d255bb0e HS	281	void spi_cs_deactivate(struct spi_slave *slave)
d255bb0e HS	282	{
6d0f6bcf	283	volatile gpio83xx_t iopd = &((immap_t )CONFIG_SYS_IMMR)->gpio[0];
80ddd226	284
d255bb0e HS	285	iopd->dat \|= SPI_CS_MASK;
d255bb0e HS	286	}
80ddd226 BW	287	#endif /* CONFIG_HARD_SPI */
80ddd226 BW	288
3fde9e8b KP	289	#if defined(CONFIG_OF_BOARD_SETUP)
3fde9e8b KP	290	void ft_board_setup(void blob, bd_t bd)
bf0b542d	291	{
3fde9e8b KP	292	ft_cpu_setup(blob, bd);
	293	#ifdef CONFIG_PCI
	294	ft_pci_setup(blob, bd);
	295	#endif
bf0b542d KP	296	}
bf0b542d KP	297	#endif