[people/ms/u-boot.git] / board / freescale / mpc8349itx / pci.c

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <asm/mmu.h>
#include <asm/global_data.h>
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8349itx_config_table[] = {
	{
	 PCI_ANY_ID,
	 PCI_ANY_ID,
	 PCI_ANY_ID,
	 PCI_ANY_ID,
	 PCI_IDSEL_NUMBER,
	 PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {
	  PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
};
#endif

static struct pci_controller pci_hose[] = {
	{
#ifndef CONFIG_PCI_PNP
	      config_table:pci_mpc8349itx_config_table,
#endif
	 },
	{
#ifndef CONFIG_PCI_PNP
	      config_table:pci_mpc8349itx_config_table,
#endif
	 }
};

/**************************************************************************
 * pci_init_board()
 *
 * NOTICE: PCI2 is not currently supported
 *
 */
void pci_init_board(void)
{
	volatile immap_t *immr;
	volatile clk83xx_t *clk;
	volatile law83xx_t *pci_law;
	volatile pot83xx_t *pci_pot;
	volatile pcictrl83xx_t *pci_ctrl;
	volatile pciconf83xx_t *pci_conf;
	u8 reg8;
	u16 reg16;
	u32 reg32;
	u32 dev;
	struct pci_controller *hose;

	immr = (immap_t *) CFG_IMMR;
	clk = (clk83xx_t *) & immr->clk;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;

	hose = &pci_hose[0];

	/*
	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	 */

	reg32 = clk->occr;
	udelay(2000);

#ifdef CONFIG_HARD_I2C
	i2c_set_bus_num(1);
	/* Read the PCI_M66EN jumper setting */
	if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
	    (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
		if (reg8 & I2C_8574_PCI66)
			clk->occr = 0xff000000;	/* 66 MHz PCI */
		else
			clk->occr = 0xff600001;	/* 33 MHz PCI */
	} else {
		clk->occr = 0xff600001;	/* 33 MHz PCI */
	}
#else
	clk->occr = 0xff000000;	/* 66 MHz PCI */
#endif

	udelay(2000);

	/*
	 * Release PCI RST Output signal
	 */
	pci_ctrl[0].gcr = 0;
	udelay(2000);
	pci_ctrl[0].gcr = 1;

#ifdef CONFIG_MPC83XX_PCI2
	pci_ctrl[1].gcr = 0;
	udelay(2000);
	pci_ctrl[1].gcr = 1;
#endif

	/* We need to wait at least a 1sec based on PCI specs */
	{
		int i;

		for (i = 0; i < 1000; i++)
			udelay(1000);
	}

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;

	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI1 mem space - prefetch */
	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;

	/* PCI1 IO space */
	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;

	/* PCI1 mmio - non-prefetch mem space */
	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
	    PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CFG_PCI1_MEM_BASE,
		       CFG_PCI1_MEM_PHYS,
		       CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CFG_PCI1_MMIO_BASE,
		       CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CFG_PCI1_IO_BASE,
		       CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);

#ifdef CONFIG_MPC83XX_PCI2
	hose = &pci_hose[1];

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI2 mem space - prefetch */
	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;

	/* PCI2 IO space */
	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;

	/* PCI2 mmio - non-prefetch mem space */
	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[1].pitar1 = 0x0;
	pci_ctrl[1].pibar1 = 0x0;
	pci_ctrl[1].piebar1 = 0x0;
	pci_ctrl[1].piwar1 =
	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
	    (__ilog2(gd->ram_size) - 1);

	hose->first_busno = pci_hose[0].last_busno + 1;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CFG_PCI2_MEM_BASE,
		       CFG_PCI2_MEM_PHYS,
		       CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CFG_PCI2_MMIO_BASE,
		       CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CFG_PCI2_IO_BASE,
		       CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
#endif
}

#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
	int nodeoffset;
	int tmp[2];
	const char *path;

	nodeoffset = fdt_path_offset(blob, "/aliases");
	if (nodeoffset >= 0) {
		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
		if (path) {
			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
			do_fixup_by_path(blob, path, "bus-range",
				&tmp, sizeof(tmp), 1);

			tmp[0] = cpu_to_be32(gd->pci_clk);
			do_fixup_by_path(blob, path, "clock-frequency",
				&tmp, sizeof(tmp[0]), 1);
		}
#ifdef CONFIG_MPC83XX_PCI2
		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
		if (path) {
			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
			do_fixup_by_path(blob, path, "bus-range",
				&tmp, sizeof(tmp), 1);

			tmp[0] = cpu_to_be32(gd->pci_clk);
			do_fixup_by_path(blob, path, "clock-frequency",
				&tmp, sizeof(tmp[0]), 1);
		}
#endif
	}
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
ft_pci_setup(void *blob, bd_t *bd)
{
       	u32 *p;
       	int len;

       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
       	if (p != NULL) {
		p[0] = pci_hose[0].first_busno;
		p[1] = pci_hose[0].last_busno;
       	}

#ifdef CONFIG_MPC83XX_PCI2
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
	if (p != NULL) {
		p[0] = pci_hose[1].first_busno;
		p[1] = pci_hose[1].last_busno;
	}
#endif
}
#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
Commit	Line	Data
2ad6b513 TT	1	/*
	2	* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24
	25	#ifdef CONFIG_PCI
	26
	27	#include <asm/mmu.h>
	28	#include <asm/global_data.h>
	29	#include <pci.h>
	30	#include <asm/mpc8349_pci.h>
	31	#include <i2c.h>
be5e6181 TT	32	#if defined(CONFIG_OF_FLAT_TREE)
be5e6181 TT	33	#include <ft_build.h>
3fde9e8b KP	34	#elif defined(CONFIG_OF_LIBFDT)
3fde9e8b KP	35	#include <libfdt.h>
5b8bc606	36	#include <fdt_support.h>
be5e6181	37	#endif
2ad6b513 TT	38
	39	DECLARE_GLOBAL_DATA_PTR;
	40
	41	/* System RAM mapped to PCI space */
	42	#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
	43	#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
	44
	45	#ifndef CONFIG_PCI_PNP
	46	static struct pci_config_table pci_mpc8349itx_config_table[] = {
	47	{
	48	PCI_ANY_ID,
	49	PCI_ANY_ID,
	50	PCI_ANY_ID,
	51	PCI_ANY_ID,
	52	PCI_IDSEL_NUMBER,
	53	PCI_ANY_ID,
	54	pci_cfgfunc_config_device,
	55	{
	56	PCI_ENET0_IOADDR,
	57	PCI_ENET0_MEMADDR,
	58	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER}
	59	},
	60	{}
	61	};
	62	#endif
	63
	64	static struct pci_controller pci_hose[] = {
	65	{
	66	#ifndef CONFIG_PCI_PNP
	67	config_table:pci_mpc8349itx_config_table,
	68	#endif
	69	},
	70	{
	71	#ifndef CONFIG_PCI_PNP
	72	config_table:pci_mpc8349itx_config_table,
	73	#endif
	74	}
	75	};
	76
	77	/**************************************************************************
	78	* pci_init_board()
	79	*
	80	* NOTICE: PCI2 is not currently supported
	81	*
	82	*/
	83	void pci_init_board(void)
	84	{
	85	volatile immap_t *immr;
	86	volatile clk83xx_t *clk;
	87	volatile law83xx_t *pci_law;
	88	volatile pot83xx_t *pci_pot;
	89	volatile pcictrl83xx_t *pci_ctrl;
	90	volatile pciconf83xx_t *pci_conf;
	91	u8 reg8;
	92	u16 reg16;
	93	u32 reg32;
	94	u32 dev;
	95	struct pci_controller *hose;
	96
d239d74b	97	immr = (immap_t *) CFG_IMMR;
2ad6b513 TT	98	clk = (clk83xx_t *) & immr->clk;
	99	pci_law = immr->sysconf.pcilaw;
	100	pci_pot = immr->ios.pot;
	101	pci_ctrl = immr->pci_ctrl;
	102	pci_conf = immr->pci_conf;
	103
	104	hose = &pci_hose[0];
	105
	106	/*
	107	* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	108	*/
	109
	110	reg32 = clk->occr;
	111	udelay(2000);
	112
	113	#ifdef CONFIG_HARD_I2C
be5e6181	114	i2c_set_bus_num(1);
2ad6b513 TT	115	/* Read the PCI_M66EN jumper setting */
	116	if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) \|\|
	117	(i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
	118	if (reg8 & I2C_8574_PCI66)
	119	clk->occr = 0xff000000; /* 66 MHz PCI */
	120	else
	121	clk->occr = 0xff600001; /* 33 MHz PCI */
	122	} else {
	123	clk->occr = 0xff600001; /* 33 MHz PCI */
	124	}
	125	#else
	126	clk->occr = 0xff000000; /* 66 MHz PCI */
	127	#endif
	128
	129	udelay(2000);
	130
	131	/*
	132	* Release PCI RST Output signal
	133	*/
	134	pci_ctrl[0].gcr = 0;
	135	udelay(2000);
	136	pci_ctrl[0].gcr = 1;
	137
	138	#ifdef CONFIG_MPC83XX_PCI2
	139	pci_ctrl[1].gcr = 0;
	140	udelay(2000);
	141	pci_ctrl[1].gcr = 1;
	142	#endif
	143
	144	/* We need to wait at least a 1sec based on PCI specs */
	145	{
	146	int i;
	147
	148	for (i = 0; i < 1000; i++)
	149	udelay(1000);
	150	}
	151
	152	/*
	153	* Configure PCI Local Access Windows
	154	*/
	155	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
	156	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_1G;
	157
	158	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
98883332	159	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_32M;
2ad6b513 TT	160
	161	/*
	162	* Configure PCI Outbound Translation Windows
	163	*/
	164
	165	/* PCI1 mem space - prefetch */
	166	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	167	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
98883332	168	pci_pot[0].pocmr = POCMR_EN \| POCMR_PREFETCH_EN \| POCMR_CM_256M;
2ad6b513 TT	169
	170	/* PCI1 IO space */
	171	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	172	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
98883332	173	pci_pot[1].pocmr = POCMR_EN \| POCMR_IO \| POCMR_CM_16M;
2ad6b513 TT	174
	175	/* PCI1 mmio - non-prefetch mem space */
	176	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
	177	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
98883332	178	pci_pot[2].pocmr = POCMR_EN \| POCMR_CM_256M;
2ad6b513 TT	179
	180	/*
	181	* Configure PCI Inbound Translation Windows
	182	*/
	183
	184	/* we need RAM mapped to PCI space for the devices to
	185	* access main memory */
	186	pci_ctrl[0].pitar1 = 0x0;
	187	pci_ctrl[0].pibar1 = 0x0;
	188	pci_ctrl[0].piebar1 = 0x0;
	189	pci_ctrl[0].piwar1 = PIWAR_EN \| PIWAR_PF \| PIWAR_RTT_SNOOP \|
	190	PIWAR_WTT_SNOOP \| (__ilog2(gd->ram_size) - 1);
	191
	192	hose->first_busno = 0;
	193	hose->last_busno = 0xff;
	194
	195	/* PCI memory prefetch space */
	196	pci_set_region(hose->regions + 0,
	197	CFG_PCI1_MEM_BASE,
	198	CFG_PCI1_MEM_PHYS,
	199	CFG_PCI1_MEM_SIZE, PCI_REGION_MEM \| PCI_REGION_PREFETCH);
	200
	201	/* PCI memory space */
	202	pci_set_region(hose->regions + 1,
	203	CFG_PCI1_MMIO_BASE,
	204	CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
	205
	206	/* PCI IO space */
	207	pci_set_region(hose->regions + 2,
	208	CFG_PCI1_IO_BASE,
	209	CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
	210
	211	/* System memory space */
	212	pci_set_region(hose->regions + 3,
	213	CONFIG_PCI_SYS_MEM_BUS,
	214	CONFIG_PCI_SYS_MEM_PHYS,
	215	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_MEMORY);
	216
	217	hose->region_count = 4;
	218
	219	pci_setup_indirect(hose,
d239d74b	220	(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
2ad6b513 TT	221
	222	pci_register_hose(hose);
	223
	224	/*
	225	* Write to Command register
	226	*/
	227	reg16 = 0xff;
	228	dev = PCI_BDF(hose->first_busno, 0, 0);
	229	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	230	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	231	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	232
	233	/*
	234	* Clear non-reserved bits in status register.
	235	*/
	236	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	237	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	238	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	239
	240	#ifdef CONFIG_PCI_SCAN_SHOW
	241	printf("PCI: Bus Dev VenId DevId Class Int\n");
	242	#endif
	243	/*
	244	* Hose scan.
	245	*/
	246	hose->last_busno = pci_hose_scan(hose);
	247
	248	#ifdef CONFIG_MPC83XX_PCI2
	249	hose = &pci_hose[1];
	250
	251	/*
	252	* Configure PCI Outbound Translation Windows
	253	*/
	254
	255	/* PCI2 mem space - prefetch */
	256	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
	257	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
98883332	258	pci_pot[3].pocmr = POCMR_EN \| POCMR_PCI2 \| POCMR_PREFETCH_EN \| POCMR_CM_256M;
2ad6b513 TT	259
	260	/* PCI2 IO space */
	261	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
	262	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
98883332	263	pci_pot[4].pocmr = POCMR_EN \| POCMR_PCI2 \| POCMR_IO \| POCMR_CM_16M;
2ad6b513 TT	264
	265	/* PCI2 mmio - non-prefetch mem space */
	266	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
	267	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
98883332	268	pci_pot[5].pocmr = POCMR_EN \| POCMR_PCI2 \| POCMR_CM_256M;
2ad6b513 TT	269
	270	/*
	271	* Configure PCI Inbound Translation Windows
	272	*/
	273
	274	/* we need RAM mapped to PCI space for the devices to
	275	* access main memory */
	276	pci_ctrl[1].pitar1 = 0x0;
	277	pci_ctrl[1].pibar1 = 0x0;
	278	pci_ctrl[1].piebar1 = 0x0;
	279	pci_ctrl[1].piwar1 =
	280	PIWAR_EN \| PIWAR_PF \| PIWAR_RTT_SNOOP \| PIWAR_WTT_SNOOP \|
	281	(__ilog2(gd->ram_size) - 1);
	282
	283	hose->first_busno = pci_hose[0].last_busno + 1;
	284	hose->last_busno = 0xff;
	285
	286	/* PCI memory prefetch space */
	287	pci_set_region(hose->regions + 0,
	288	CFG_PCI2_MEM_BASE,
	289	CFG_PCI2_MEM_PHYS,
	290	CFG_PCI2_MEM_SIZE, PCI_REGION_MEM \| PCI_REGION_PREFETCH);
	291
	292	/* PCI memory space */
	293	pci_set_region(hose->regions + 1,
	294	CFG_PCI2_MMIO_BASE,
	295	CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
	296
	297	/* PCI IO space */
	298	pci_set_region(hose->regions + 2,
	299	CFG_PCI2_IO_BASE,
	300	CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
	301
	302	/* System memory space */
	303	pci_set_region(hose->regions + 3,
	304	CONFIG_PCI_SYS_MEM_BUS,
	305	CONFIG_PCI_SYS_MEM_PHYS,
	306	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_MEMORY);
	307
	308	hose->region_count = 4;
	309
	310	pci_setup_indirect(hose,
d239d74b	311	(CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
2ad6b513 TT	312
	313	pci_register_hose(hose);
	314
	315	/*
	316	* Write to Command register
	317	*/
	318	reg16 = 0xff;
	319	dev = PCI_BDF(hose->first_busno, 0, 0);
	320	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	321	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	322	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	323
	324	/*
	325	* Clear non-reserved bits in status register.
	326	*/
	327	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	328	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	329	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	330
	331	/*
	332	* Hose scan.
	333	*/
	334	hose->last_busno = pci_hose_scan(hose);
	335	#endif
	336	}
	337
3fde9e8b	338	#if defined(CONFIG_OF_LIBFDT)
5b8bc606	339	void ft_pci_setup(void blob, bd_t bd)
3fde9e8b KP	340	{
3fde9e8b KP	341	int nodeoffset;
3fde9e8b	342	int tmp[2];
5b8bc606	343	const char *path;
3fde9e8b	344
5b8bc606	345	nodeoffset = fdt_path_offset(blob, "/aliases");
3fde9e8b	346	if (nodeoffset >= 0) {
5b8bc606 KP	347	path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
	348	if (path) {
	349	tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
	350	tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
	351	do_fixup_by_path(blob, path, "bus-range",
	352	&tmp, sizeof(tmp), 1);
	353
	354	tmp[0] = cpu_to_be32(gd->pci_clk);
	355	do_fixup_by_path(blob, path, "clock-frequency",
	356	&tmp, sizeof(tmp[0]), 1);
	357	}
3fde9e8b	358	#ifdef CONFIG_MPC83XX_PCI2
5b8bc606 KP	359	path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
	360	if (path) {
	361	tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
	362	tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
	363	do_fixup_by_path(blob, path, "bus-range",
	364	&tmp, sizeof(tmp), 1);
	365
	366	tmp[0] = cpu_to_be32(gd->pci_clk);
	367	do_fixup_by_path(blob, path, "clock-frequency",
	368	&tmp, sizeof(tmp[0]), 1);
	369	}
3fde9e8b	370	#endif
5b8bc606	371	}
3fde9e8b KP	372	}
3fde9e8b KP	373	#elif defined(CONFIG_OF_FLAT_TREE)
bf0b542d KP	374	void
	375	ft_pci_setup(void blob, bd_t bd)
	376	{
	377	u32 *p;
	378	int len;
	379
	380	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
	381	if (p != NULL) {
	382	p[0] = pci_hose[0].first_busno;
	383	p[1] = pci_hose[0].last_busno;
	384	}
	385
	386	#ifdef CONFIG_MPC83XX_PCI2
	387	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
	388	if (p != NULL) {
	389	p[0] = pci_hose[1].first_busno;
	390	p[1] = pci_hose[1].last_busno;
	391	}
	392	#endif
	393	}
	394	#endif /* CONFIG_OF_FLAT_TREE */
3fde9e8b	395	#endif /* CONFIG_PCI */