[people/ms/u-boot.git] / board / freescale / mpc8360emds / mpc8360emds.c

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#else
#include <asm/mmu.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{0,  3, 1, 0, 1}, /* TxD0 */
	{0,  4, 1, 0, 1}, /* TxD1 */
	{0,  5, 1, 0, 1}, /* TxD2 */
	{0,  6, 1, 0, 1}, /* TxD3 */
	{1,  6, 1, 0, 3}, /* TxD4 */
	{1,  7, 1, 0, 1}, /* TxD5 */
	{1,  9, 1, 0, 2}, /* TxD6 */
	{1, 10, 1, 0, 2}, /* TxD7 */
	{0,  9, 2, 0, 1}, /* RxD0 */
	{0, 10, 2, 0, 1}, /* RxD1 */
	{0, 11, 2, 0, 1}, /* RxD2 */
	{0, 12, 2, 0, 1}, /* RxD3 */
	{0, 13, 2, 0, 1}, /* RxD4 */
	{1,  1, 2, 0, 2}, /* RxD5 */
	{1,  0, 2, 0, 2}, /* RxD6 */
	{1,  4, 2, 0, 2}, /* RxD7 */
	{0,  7, 1, 0, 1}, /* TX_EN */
	{0,  8, 1, 0, 1}, /* TX_ER */
	{0, 15, 2, 0, 1}, /* RX_DV */
	{0, 16, 2, 0, 1}, /* RX_ER */
	{0,  0, 2, 0, 1}, /* RX_CLK */
	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
	/* GETH2 */
	{0, 17, 1, 0, 1}, /* TxD0 */
	{0, 18, 1, 0, 1}, /* TxD1 */
	{0, 19, 1, 0, 1}, /* TxD2 */
	{0, 20, 1, 0, 1}, /* TxD3 */
	{1,  2, 1, 0, 1}, /* TxD4 */
	{1,  3, 1, 0, 2}, /* TxD5 */
	{1,  5, 1, 0, 3}, /* TxD6 */
	{1,  8, 1, 0, 3}, /* TxD7 */
	{0, 23, 2, 0, 1}, /* RxD0 */
	{0, 24, 2, 0, 1}, /* RxD1 */
	{0, 25, 2, 0, 1}, /* RxD2 */
	{0, 26, 2, 0, 1}, /* RxD3 */
	{0, 27, 2, 0, 1}, /* RxD4 */
	{1, 12, 2, 0, 2}, /* RxD5 */
	{1, 13, 2, 0, 3}, /* RxD6 */
	{1, 11, 2, 0, 2}, /* RxD7 */
	{0, 21, 1, 0, 1}, /* TX_EN */
	{0, 22, 1, 0, 1}, /* TX_ER */
	{0, 29, 2, 0, 1}, /* RX_DV */
	{0, 30, 2, 0, 1}, /* RX_ER */
	{0, 31, 2, 0, 1}, /* RX_CLK */
	{2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */

	{0,  1, 3, 0, 2}, /* MDIO */
	{0,  2, 1, 0, 1}, /* MDC */

	{5,  0, 1, 0, 2}, /* UART2_SOUT */
	{5,  1, 2, 0, 3}, /* UART2_CTS */
	{5,  2, 1, 0, 1}, /* UART2_RTS */
	{5,  3, 2, 0, 2}, /* UART2_SIN */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

int board_early_init_f(void)
{

	u8 *bcsr = (u8 *)CFG_BCSR;
	const immap_t *immr = (immap_t *)CFG_IMMR;

	/* Enable flash write */
	bcsr[0xa] &= ~0x04;

	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
	if (immr->sysconf.spridr == SPR_8360_REV20 ||
	    immr->sysconf.spridr == SPR_8360E_REV20 ||
	    immr->sysconf.spridr == SPR_8360_REV21 ||
	    immr->sysconf.spridr == SPR_8360E_REV21)
		bcsr[0xe] = 0x30;

	/* Enable second UART */
	bcsr[0x9] &= ~0x01;

	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
	pib_init();
#endif
	return 0;
}

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
void sdram_init(void);

long int initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	/*
	 * Initialize DDR ECC byte
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CFG_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].ar =
	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CFG_DDR_MODE;
	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
#else
	im->ddr.csbnds[0].csbnds = 0x00000007;
	im->ddr.csbnds[1].csbnds = 0x0008000f;

	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
	im->ddr.cs_config[1] = CFG_DDR_CONFIG;

	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
	im->ddr.sdram_cfg = CFG_DDR_CONTROL;

	im->ddr.sdram_mode = CFG_DDR_MODE;
	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
#endif
	udelay(200);
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;

	return msize;
}
#endif				/*!CFG_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC8360EMDS\n");
	return 0;
}

/*
 * if MPC8360EMDS is soldered with SDRAM
 */
#if defined(CFG_BR2_PRELIM)  \
	&& defined(CFG_OR2_PRELIM) \
	&& defined(CFG_LBLAWBAR2_PRELIM) \
	&& defined(CFG_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile lbus83xx_t *lbc = &immap->lbus;
	uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */
	/*setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CFG_LBC_LBCR;
	lbc->mrtpr = CFG_LBC_MRTPR;
	lbc->lsrt = CFG_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CFG_LBC_LSDMR_5;	/* Normal Operation */
	lbc->lsdmr = CFG_LBC_LSDMR_1;	/* Precharge All Banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * We need do 8 times auto refresh operation.
	 */
	lbc->lsdmr = CFG_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;	/* 1 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 2 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 3 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 4 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 5 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 6 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 7 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 8 times */
	udelay(100);

	/* Mode register write operation */
	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	*(sdram_addr + 0xcc) = 0xff;
	udelay(100);

	/* Normal operation */
	lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	const immap_t *immr = (immap_t *)CFG_IMMR;
#if defined(CONFIG_OF_FLAT_TREE)
	u32 *p;
	int len;

	p = ft_get_prop(blob, "/memory/reg", &len);
	if (p != NULL) {
		*p++ = cpu_to_be32(bd->bi_memstart);
		*p = cpu_to_be32(bd->bi_memsize);
	}
#endif
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	/*
	 * mpc8360ea pb mds errata 2: RGMII timing
	 * if on mpc8360ea rev. 2.1,
	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	 */
	if (immr->sysconf.spridr == SPR_8360_REV21 ||
	    immr->sysconf.spridr == SPR_8360E_REV21) {
		int nodeoffset;
		const char *prop;

		/* fixup UCC 1 if using rgmii-id mode */
		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@2000");
		if (nodeoffset >= 0) {
			prop = fdt_getprop(blob, nodeoffset,
					        "phy-connection-type", 0);
			if (prop && (strcmp(prop, "rgmii-id") == 0))
				fdt_setprop(blob, nodeoffset, "phy-connection-type",
					    "rgmii-rxid", sizeof("rgmii-rxid"));
		}

		/* fixup UCC 2 if using rgmii-id mode */
		nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@3000");
		if (nodeoffset >= 0) {
			prop = fdt_getprop(blob, nodeoffset,
					        "phy-connection-type", 0);
			if (prop && (strcmp(prop, "rgmii-id") == 0))
				fdt_setprop(blob, nodeoffset, "phy-connection-type",
					    "rgmii-rxid", sizeof("rgmii-rxid"));
		}
	}
}
#endif
Commit	Line	Data
5f820439 DL	1	/*
5f820439 DL	2	* Copyright (C) 2006 Freescale Semiconductor, Inc.
5f820439	3	* Dave Liu <daveliu@freescale.com>
5f820439 DL	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*/
	13
	14	#include <common.h>
	15	#include <ioports.h>
	16	#include <mpc83xx.h>
	17	#include <i2c.h>
	18	#include <spd.h>
	19	#include <miiphy.h>
5f820439 DL	20	#if defined(CONFIG_PCI)
	21	#include <pci.h>
	22	#endif
	23	#if defined(CONFIG_SPD_EEPROM)
	24	#include <spd_sdram.h>
	25	#else
	26	#include <asm/mmu.h>
	27	#endif
bf0b542d KP	28	#if defined(CONFIG_OF_FLAT_TREE)
bf0b542d KP	29	#include <ft_build.h>
26d02c9b	30	#elif defined(CONFIG_OF_LIBFDT)
213bf8c8	31	#include <libfdt.h>
213bf8c8	32	#endif
14778585	33	#if defined(CONFIG_PQ_MDS_PIB)
e58fe957	34	#include "../common/pq-mds-pib.h"
14778585	35	#endif
5f820439	36
7737d5c6 DL	37	const qe_iop_conf_t qe_iop_conf_tab[] = {
	38	/* GETH1 */
	39	{0, 3, 1, 0, 1}, /* TxD0 */
	40	{0, 4, 1, 0, 1}, /* TxD1 */
	41	{0, 5, 1, 0, 1}, /* TxD2 */
	42	{0, 6, 1, 0, 1}, /* TxD3 */
	43	{1, 6, 1, 0, 3}, /* TxD4 */
	44	{1, 7, 1, 0, 1}, /* TxD5 */
	45	{1, 9, 1, 0, 2}, /* TxD6 */
	46	{1, 10, 1, 0, 2}, /* TxD7 */
	47	{0, 9, 2, 0, 1}, /* RxD0 */
	48	{0, 10, 2, 0, 1}, /* RxD1 */
	49	{0, 11, 2, 0, 1}, /* RxD2 */
	50	{0, 12, 2, 0, 1}, /* RxD3 */
	51	{0, 13, 2, 0, 1}, /* RxD4 */
	52	{1, 1, 2, 0, 2}, /* RxD5 */
	53	{1, 0, 2, 0, 2}, /* RxD6 */
	54	{1, 4, 2, 0, 2}, /* RxD7 */
	55	{0, 7, 1, 0, 1}, /* TX_EN */
	56	{0, 8, 1, 0, 1}, /* TX_ER */
	57	{0, 15, 2, 0, 1}, /* RX_DV */
	58	{0, 16, 2, 0, 1}, /* RX_ER */
	59	{0, 0, 2, 0, 1}, /* RX_CLK */
	60	{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	61	{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
	62	/* GETH2 */
	63	{0, 17, 1, 0, 1}, /* TxD0 */
	64	{0, 18, 1, 0, 1}, /* TxD1 */
	65	{0, 19, 1, 0, 1}, /* TxD2 */
	66	{0, 20, 1, 0, 1}, /* TxD3 */
	67	{1, 2, 1, 0, 1}, /* TxD4 */
	68	{1, 3, 1, 0, 2}, /* TxD5 */
	69	{1, 5, 1, 0, 3}, /* TxD6 */
	70	{1, 8, 1, 0, 3}, /* TxD7 */
	71	{0, 23, 2, 0, 1}, /* RxD0 */
	72	{0, 24, 2, 0, 1}, /* RxD1 */
	73	{0, 25, 2, 0, 1}, /* RxD2 */
	74	{0, 26, 2, 0, 1}, /* RxD3 */
	75	{0, 27, 2, 0, 1}, /* RxD4 */
	76	{1, 12, 2, 0, 2}, /* RxD5 */
	77	{1, 13, 2, 0, 3}, /* RxD6 */
	78	{1, 11, 2, 0, 2}, /* RxD7 */
	79	{0, 21, 1, 0, 1}, /* TX_EN */
	80	{0, 22, 1, 0, 1}, /* TX_ER */
	81	{0, 29, 2, 0, 1}, /* RX_DV */
	82	{0, 30, 2, 0, 1}, /* RX_ER */
	83	{0, 31, 2, 0, 1}, /* RX_CLK */
	84	{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	85	{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
	86
	87	{0, 1, 3, 0, 2}, /* MDIO */
	88	{0, 2, 1, 0, 1}, /* MDC */
	89
651d96f7 AV	90	{5, 0, 1, 0, 2}, /* UART2_SOUT */
	91	{5, 1, 2, 0, 3}, /* UART2_CTS */
	92	{5, 2, 1, 0, 1}, /* UART2_RTS */
	93	{5, 3, 2, 0, 2}, /* UART2_SIN */
	94
7737d5c6 DL	95	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	96	};
	97
5f820439 DL	98	int board_early_init_f(void)
5f820439 DL	99	{
3fc0bd15 KP	100
	101	u8 bcsr = (u8 )CFG_BCSR;
	102	const immap_t immr = (immap_t )CFG_IMMR;
5f820439 DL	103
	104	/* Enable flash write */
	105	bcsr[0xa] &= ~0x04;
	106
3fc0bd15 KP	107	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
3fc0bd15 KP	108	if (immr->sysconf.spridr == SPR_8360_REV20 \|\|
1ded0242 LN	109	immr->sysconf.spridr == SPR_8360E_REV20 \|\|
	110	immr->sysconf.spridr == SPR_8360_REV21 \|\|
	111	immr->sysconf.spridr == SPR_8360E_REV21)
3fc0bd15 KP	112	bcsr[0xe] = 0x30;
3fc0bd15 KP	113
651d96f7 AV	114	/* Enable second UART */
	115	bcsr[0x9] &= ~0x01;
	116
5f820439 DL	117	return 0;
	118	}
	119
14778585 TL	120	int board_early_init_r(void)
	121	{
	122	#ifdef CONFIG_PQ_MDS_PIB
	123	pib_init();
	124	#endif
	125	return 0;
	126	}
	127
5f820439 DL	128	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	129	extern void ddr_enable_ecc(unsigned int dram_size);
	130	#endif
	131	int fixed_sdram(void);
	132	void sdram_init(void);
	133
	134	long int initdram(int board_type)
	135	{
d239d74b	136	volatile immap_t im = (immap_t ) CFG_IMMR;
5f820439 DL	137	u32 msize = 0;
	138
	139	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	140	return -1;
	141
	142	/* DDR SDRAM - Main SODIMM */
	143	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
	144	#if defined(CONFIG_SPD_EEPROM)
	145	msize = spd_sdram();
	146	#else
	147	msize = fixed_sdram();
	148	#endif
	149
	150	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	151	/*
	152	* Initialize DDR ECC byte
	153	*/
	154	ddr_enable_ecc(msize * 1024 * 1024);
	155	#endif
	156	/*
	157	* Initialize SDRAM if it is on local bus.
	158	*/
	159	sdram_init();
bbea46f7	160
5f820439 DL	161	/* return total bus SDRAM size(bytes) -- DDR */
	162	return (msize * 1024 * 1024);
	163	}
	164
	165	#if !defined(CONFIG_SPD_EEPROM)
	166	/*************************************************************************
	167	* fixed sdram init -- doesn't use serial presence detect.
	168	************************************************************************/
	169	int fixed_sdram(void)
	170	{
d239d74b	171	volatile immap_t im = (immap_t ) CFG_IMMR;
5f820439 DL	172	u32 msize = 0;
	173	u32 ddr_size;
	174	u32 ddr_size_log2;
	175
	176	msize = CFG_DDR_SIZE;
	177	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	178	(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
	179	if (ddr_size & 1) {
	180	return -1;
	181	}
	182	}
	183	im->sysconf.ddrlaw[0].ar =
	184	LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
	185	#if (CFG_DDR_SIZE != 256)
	186	#warning Currenly any ddr size other than 256 is not supported
	187	#endif
d61853cf XX	188	#ifdef CONFIG_DDR_II
	189	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
	190	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
	191	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
	192	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	193	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
	194	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
	195	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
	196	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
	197	im->ddr.sdram_mode = CFG_DDR_MODE;
	198	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
	199	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
	200	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
	201	#else
5f820439 DL	202	im->ddr.csbnds[0].csbnds = 0x00000007;
	203	im->ddr.csbnds[1].csbnds = 0x0008000f;
	204
	205	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
	206	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
	207
	208	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	209	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
	210	im->ddr.sdram_cfg = CFG_DDR_CONTROL;
	211
	212	im->ddr.sdram_mode = CFG_DDR_MODE;
	213	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
d61853cf	214	#endif
5f820439 DL	215	udelay(200);
	216	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	217
	218	return msize;
	219	}
	220	#endif /!CFG_SPD_EEPROM /
	221
	222	int checkboard(void)
	223	{
	224	puts("Board: Freescale MPC8360EMDS\n");
	225	return 0;
	226	}
	227
	228	/*
	229	* if MPC8360EMDS is soldered with SDRAM
	230	*/
	231	#if defined(CFG_BR2_PRELIM) \
	232	&& defined(CFG_OR2_PRELIM) \
	233	&& defined(CFG_LBLAWBAR2_PRELIM) \
	234	&& defined(CFG_LBLAWAR2_PRELIM)
	235	/*
	236	* Initialize SDRAM memory on the Local Bus.
	237	*/
	238
	239	void sdram_init(void)
	240	{
d239d74b	241	volatile immap_t immap = (immap_t ) CFG_IMMR;
5f820439 DL	242	volatile lbus83xx_t *lbc = &immap->lbus;
	243	uint sdram_addr = (uint ) CFG_LBC_SDRAM_BASE;
	244
5f820439 DL	245	/*
	246	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	247	*/
	248	/setup mtrpt, lsrt and lbcr for LB bus /
	249	lbc->lbcr = CFG_LBC_LBCR;
	250	lbc->mrtpr = CFG_LBC_MRTPR;
	251	lbc->lsrt = CFG_LBC_LSRT;
	252	asm("sync");
	253
	254	/*
	255	* Configure the SDRAM controller Machine Mode Register.
	256	*/
	257	lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
	258	lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
	259	asm("sync");
	260	*sdram_addr = 0xff;
	261	udelay(100);
	262
	263	/*
	264	* We need do 8 times auto refresh operation.
	265	*/
	266	lbc->lsdmr = CFG_LBC_LSDMR_2;
	267	asm("sync");
	268	sdram_addr = 0xff; / 1 times */
	269	udelay(100);
	270	sdram_addr = 0xff; / 2 times */
	271	udelay(100);
	272	sdram_addr = 0xff; / 3 times */
	273	udelay(100);
	274	sdram_addr = 0xff; / 4 times */
	275	udelay(100);
	276	sdram_addr = 0xff; / 5 times */
	277	udelay(100);
	278	sdram_addr = 0xff; / 6 times */
	279	udelay(100);
	280	sdram_addr = 0xff; / 7 times */
	281	udelay(100);
	282	sdram_addr = 0xff; / 8 times */
	283	udelay(100);
	284
	285	/* Mode register write operation */
	286	lbc->lsdmr = CFG_LBC_LSDMR_4;
	287	asm("sync");
	288	*(sdram_addr + 0xcc) = 0xff;
	289	udelay(100);
	290
	291	/* Normal operation */
	292	lbc->lsdmr = CFG_LBC_LSDMR_5 \| 0x40000000;
	293	asm("sync");
	294	*sdram_addr = 0xff;
	295	udelay(100);
	296	}
	297	#else
	298	void sdram_init(void)
	299	{
5f820439 DL	300	}
	301	#endif
	302
3fde9e8b KP	303	#if defined(CONFIG_OF_BOARD_SETUP)
3fde9e8b KP	304	void ft_board_setup(void blob, bd_t bd)
bf0b542d	305	{
24f86843	306	const immap_t immr = (immap_t )CFG_IMMR;
6a16e0df	307	#if defined(CONFIG_OF_FLAT_TREE)
bf0b542d KP	308	u32 *p;
	309	int len;
	310
bf0b542d KP	311	p = ft_get_prop(blob, "/memory/reg", &len);
	312	if (p != NULL) {
	313	*p++ = cpu_to_be32(bd->bi_memstart);
	314	*p = cpu_to_be32(bd->bi_memsize);
	315	}
213bf8c8	316	#endif
3fde9e8b	317	ft_cpu_setup(blob, bd);
213bf8c8 GVB	318	#ifdef CONFIG_PCI
	319	ft_pci_setup(blob, bd);
	320	#endif
24f86843 KP	321	/*
	322	* mpc8360ea pb mds errata 2: RGMII timing
	323	* if on mpc8360ea rev. 2.1,
	324	* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	325	*/
	326	if (immr->sysconf.spridr == SPR_8360_REV21 \|\|
	327	immr->sysconf.spridr == SPR_8360E_REV21) {
	328	int nodeoffset;
f602082b	329	const char *prop;
24f86843 KP	330
24f86843 KP	331	/* fixup UCC 1 if using rgmii-id mode */
c16e44fa	332	nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@2000");
24f86843 KP	333	if (nodeoffset >= 0) {
	334	prop = fdt_getprop(blob, nodeoffset,
	335	"phy-connection-type", 0);
	336	if (prop && (strcmp(prop, "rgmii-id") == 0))
	337	fdt_setprop(blob, nodeoffset, "phy-connection-type",
	338	"rgmii-rxid", sizeof("rgmii-rxid"));
	339	}
	340
	341	/* fixup UCC 2 if using rgmii-id mode */
c16e44fa	342	nodeoffset = fdt_path_offset(blob, "/" OF_QE "/ucc@3000");
24f86843 KP	343	if (nodeoffset >= 0) {
	344	prop = fdt_getprop(blob, nodeoffset,
	345	"phy-connection-type", 0);
	346	if (prop && (strcmp(prop, "rgmii-id") == 0))
	347	fdt_setprop(blob, nodeoffset, "phy-connection-type",
	348	"rgmii-rxid", sizeof("rgmii-rxid"));
	349	}
	350	}
bf0b542d	351	}
3fde9e8b	352	#endif