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5f820439 | 1 | /* |
9993e196 | 2 | * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. |
5f820439 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
5f820439 DL |
5 | */ |
6 | ||
7 | /* | |
8 | * PCI Configuration space access support for MPC83xx PCI Bridge | |
9 | */ | |
9993e196 | 10 | |
5f820439 DL |
11 | #include <asm/mmu.h> |
12 | #include <asm/io.h> | |
13 | #include <common.h> | |
9993e196 | 14 | #include <mpc83xx.h> |
5f820439 DL |
15 | #include <pci.h> |
16 | #include <i2c.h> | |
be5e6181 | 17 | #include <asm/fsl_i2c.h> |
9993e196 | 18 | #include "../common/pq-mds-pib.h" |
5f820439 DL |
19 | |
20 | DECLARE_GLOBAL_DATA_PTR; | |
21 | ||
9993e196 KP |
22 | static struct pci_region pci1_regions[] = { |
23 | { | |
24 | bus_start: CONFIG_SYS_PCI1_MEM_BASE, | |
25 | phys_start: CONFIG_SYS_PCI1_MEM_PHYS, | |
26 | size: CONFIG_SYS_PCI1_MEM_SIZE, | |
27 | flags: PCI_REGION_MEM | PCI_REGION_PREFETCH | |
28 | }, | |
29 | { | |
30 | bus_start: CONFIG_SYS_PCI1_IO_BASE, | |
31 | phys_start: CONFIG_SYS_PCI1_IO_PHYS, | |
32 | size: CONFIG_SYS_PCI1_IO_SIZE, | |
33 | flags: PCI_REGION_IO | |
34 | }, | |
35 | { | |
36 | bus_start: CONFIG_SYS_PCI1_MMIO_BASE, | |
37 | phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, | |
38 | size: CONFIG_SYS_PCI1_MMIO_SIZE, | |
39 | flags: PCI_REGION_MEM | |
40 | }, | |
41 | }; | |
5f820439 | 42 | |
9993e196 KP |
43 | #ifdef CONFIG_MPC83XX_PCI2 |
44 | static struct pci_region pci2_regions[] = { | |
5f820439 | 45 | { |
9993e196 KP |
46 | bus_start: CONFIG_SYS_PCI2_MEM_BASE, |
47 | phys_start: CONFIG_SYS_PCI2_MEM_PHYS, | |
48 | size: CONFIG_SYS_PCI2_MEM_SIZE, | |
49 | flags: PCI_REGION_MEM | PCI_REGION_PREFETCH | |
50 | }, | |
5f820439 | 51 | { |
9993e196 KP |
52 | bus_start: CONFIG_SYS_PCI2_IO_BASE, |
53 | phys_start: CONFIG_SYS_PCI2_IO_PHYS, | |
54 | size: CONFIG_SYS_PCI2_IO_SIZE, | |
55 | flags: PCI_REGION_IO | |
56 | }, | |
57 | { | |
58 | bus_start: CONFIG_SYS_PCI2_MMIO_BASE, | |
59 | phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, | |
60 | size: CONFIG_SYS_PCI2_MMIO_SIZE, | |
61 | flags: PCI_REGION_MEM | |
62 | }, | |
5f820439 | 63 | }; |
9993e196 | 64 | #endif |
5f820439 | 65 | |
5f820439 DL |
66 | void pci_init_board(void) |
67 | #ifdef CONFIG_PCISLAVE | |
68 | { | |
9993e196 KP |
69 | volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
70 | volatile law83xx_t *pci_law = immr->sysconf.pcilaw; | |
71 | volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; | |
72 | struct pci_region *reg[] = { pci1_regions }; | |
73 | ||
74 | /* Configure PCI Local Access Windows */ | |
75 | pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; | |
76 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; | |
77 | ||
78 | pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; | |
79 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; | |
80 | ||
6aa3d3bf | 81 | mpc83xx_pci_init(1, reg); |
5f820439 | 82 | |
5f820439 DL |
83 | /* |
84 | * Configure PCI Inbound Translation Windows | |
85 | */ | |
86 | pci_ctrl[0].pitar0 = 0x0; | |
87 | pci_ctrl[0].pibar0 = 0x0; | |
88 | pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | | |
89 | PIWAR_WTT_SNOOP | PIWAR_IWS_4K; | |
90 | ||
91 | pci_ctrl[0].pitar1 = 0x0; | |
92 | pci_ctrl[0].pibar1 = 0x0; | |
93 | pci_ctrl[0].piebar1 = 0x0; | |
94 | pci_ctrl[0].piwar1 &= ~PIWAR_EN; | |
95 | ||
96 | pci_ctrl[0].pitar2 = 0x0; | |
97 | pci_ctrl[0].pibar2 = 0x0; | |
98 | pci_ctrl[0].piebar2 = 0x0; | |
99 | pci_ctrl[0].piwar2 &= ~PIWAR_EN; | |
100 | ||
9993e196 KP |
101 | /* Unlock the configuration bit */ |
102 | mpc83xx_pcislave_unlock(0); | |
103 | printf("PCI: Agent mode enabled\n"); | |
5f820439 DL |
104 | } |
105 | #else | |
106 | { | |
9993e196 KP |
107 | volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
108 | volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; | |
109 | volatile law83xx_t *pci_law = immr->sysconf.pcilaw; | |
110 | #ifndef CONFIG_MPC83XX_PCI2 | |
111 | struct pci_region *reg[] = { pci1_regions }; | |
112 | #else | |
113 | struct pci_region *reg[] = { pci1_regions, pci2_regions }; | |
114 | #endif | |
5f820439 | 115 | |
9993e196 KP |
116 | /* initialize the PCA9555PW IO expander on the PIB board */ |
117 | pib_init(); | |
5f820439 | 118 | |
2ae18241 | 119 | #if defined(CONFIG_PCI_66M) |
5f820439 DL |
120 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
121 | printf("PCI clock is 66MHz\n"); | |
2ae18241 | 122 | #elif defined(CONFIG_PCI_33M) |
5f820439 DL |
123 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
124 | OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; | |
125 | printf("PCI clock is 33MHz\n"); | |
126 | #else | |
127 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; | |
128 | printf("PCI clock is 66MHz\n"); | |
129 | #endif | |
130 | udelay(2000); | |
131 | ||
9993e196 KP |
132 | /* Configure PCI Local Access Windows */ |
133 | pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; | |
5f820439 DL |
134 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
135 | ||
9993e196 | 136 | pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
5f820439 DL |
137 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
138 | ||
5f820439 DL |
139 | udelay(2000); |
140 | ||
9993e196 | 141 | #ifndef CONFIG_MPC83XX_PCI2 |
6aa3d3bf | 142 | mpc83xx_pci_init(1, reg); |
9993e196 | 143 | #else |
6aa3d3bf | 144 | mpc83xx_pci_init(2, reg); |
9993e196 | 145 | #endif |
5f820439 DL |
146 | } |
147 | #endif /* CONFIG_PCISLAVE */ |