[people/ms/u-boot.git] / board / freescale / mpc837xemds / mpc837xemds.c

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 *
 * CREDITS: Kim Phillips contribute to LIBFDT code
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif

int board_early_init_f(void)
{
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;

	/* Enable flash write */
	bcsr[0x9] &= ~0x04;
	/* Clear all of the interrupt of BCSR */
	bcsr[0xe] = 0xff;

#ifdef CONFIG_FSL_SERDES
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	u32 spridr = in_be32(&immr->sysconf.spridr);

	/* we check only part num, and don't look for CPU revisions */
	switch (PARTID_NO_E(spridr)) {
	case SPR_8377:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	case SPR_8378:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	case SPR_8379:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	default:
		printf("serdes not configured: unknown CPU part number: "
		       "%04x\n", spridr >> 16);
		break;
	}
#endif /* CONFIG_FSL_SERDES */
	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
	pib_init();
#endif
	return 0;
}

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif

	/* return total bus DDR size(bytes) */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
	u32 msize_log2 = __ilog2(msize);

	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);

#if (CONFIG_SYS_DDR_SIZE != 512)
#warning Currenly any ddr size other than 512 is not supported
#endif
	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
	udelay(50000);

	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
	udelay(1000);

	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	udelay(1000);

	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	__asm__ __volatile__("sync");
	udelay(1000);

	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	udelay(2000);
	return CONFIG_SYS_DDR_SIZE;
}
#endif /*!CONFIG_SYS_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC837xEMDS\n");
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
19580e66 DL	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	* Dave Liu <daveliu@freescale.com>
	4	*
	5	* CREDITS: Kim Phillips contribute to LIBFDT code
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*/
	12
	13	#include <common.h>
	14	#include <i2c.h>
6f8c85e8 DL	15	#include <asm/io.h>
6f8c85e8 DL	16	#include <asm/fsl_serdes.h>
19580e66	17	#include <spd_sdram.h>
b3458d2c	18	#if defined(CONFIG_OF_LIBFDT)
19580e66 DL	19	#include <libfdt.h>
	20	#endif
	21	#if defined(CONFIG_PQ_MDS_PIB)
	22	#include "../common/pq-mds-pib.h"
	23	#endif
	24
	25	int board_early_init_f(void)
	26	{
6d0f6bcf	27	u8 bcsr = (u8 )CONFIG_SYS_BCSR;
19580e66 DL	28
	29	/* Enable flash write */
	30	bcsr[0x9] &= ~0x04;
	31	/* Clear all of the interrupt of BCSR */
	32	bcsr[0xe] = 0xff;
	33
6f8c85e8	34	#ifdef CONFIG_FSL_SERDES
6d0f6bcf	35	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
6f8c85e8 DL	36	u32 spridr = in_be32(&immr->sysconf.spridr);
	37
	38	/* we check only part num, and don't look for CPU revisions */
5fb5a689	39	switch (PARTID_NO_E(spridr)) {
e5c4ade4	40	case SPR_8377:
6f8c85e8 DL	41	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
6f8c85e8 DL	42	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
e5c4ade4	43	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
6f8c85e8 DL	44	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
6f8c85e8 DL	45	break;
e5c4ade4	46	case SPR_8378:
6f8c85e8 DL	47	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
	48	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	49	break;
e5c4ade4	50	case SPR_8379:
6f8c85e8 DL	51	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
6f8c85e8 DL	52	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
e5c4ade4	53	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
6f8c85e8 DL	54	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	55	break;
	56	default:
	57	printf("serdes not configured: unknown CPU part number: "
	58	"%04x\n", spridr >> 16);
	59	break;
	60	}
	61	#endif /* CONFIG_FSL_SERDES */
19580e66 DL	62	return 0;
	63	}
	64
	65	int board_early_init_r(void)
	66	{
	67	#ifdef CONFIG_PQ_MDS_PIB
	68	pib_init();
	69	#endif
	70	return 0;
	71	}
	72
	73	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	74	extern void ddr_enable_ecc(unsigned int dram_size);
	75	#endif
	76	int fixed_sdram(void);
	77
9973e3c6	78	phys_size_t initdram(int board_type)
19580e66	79	{
6d0f6bcf	80	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
19580e66 DL	81	u32 msize = 0;
	82
	83	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	84	return -1;
	85
	86	#if defined(CONFIG_SPD_EEPROM)
	87	msize = spd_sdram();
	88	#else
	89	msize = fixed_sdram();
	90	#endif
	91
	92	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	93	/* Initialize DDR ECC byte */
	94	ddr_enable_ecc(msize * 1024 * 1024);
	95	#endif
	96
	97	/* return total bus DDR size(bytes) */
	98	return (msize * 1024 * 1024);
	99	}
	100
	101	#if !defined(CONFIG_SPD_EEPROM)
	102	/*************************************************************************
	103	* fixed sdram init -- doesn't use serial presence detect.
	104	************************************************************************/
	105	int fixed_sdram(void)
	106	{
6d0f6bcf JCPV	107	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
6d0f6bcf JCPV	108	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
19580e66 DL	109	u32 msize_log2 = __ilog2(msize);
19580e66 DL	110
6d0f6bcf	111	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
19580e66 DL	112	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN \| (msize_log2 - 1);
19580e66 DL	113
6d0f6bcf	114	#if (CONFIG_SYS_DDR_SIZE != 512)
19580e66 DL	115	#warning Currenly any ddr size other than 512 is not supported
19580e66 DL	116	#endif
6d0f6bcf	117	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
19580e66 DL	118	udelay(50000);
19580e66 DL	119
6d0f6bcf	120	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
19580e66 DL	121	udelay(1000);
19580e66 DL	122
6d0f6bcf JCPV	123	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	124	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
19580e66 DL	125	udelay(1000);
19580e66 DL	126
6d0f6bcf JCPV	127	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	128	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	129	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	130	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	131	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	132	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	133	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	134	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	135	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
19580e66 DL	136	__asm__ __volatile__("sync");
	137	udelay(1000);
	138
	139	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	140	udelay(2000);
6d0f6bcf	141	return CONFIG_SYS_DDR_SIZE;
19580e66	142	}
6d0f6bcf	143	#endif /!CONFIG_SYS_SPD_EEPROM /
19580e66 DL	144
	145	int checkboard(void)
	146	{
	147	puts("Board: Freescale MPC837xEMDS\n");
	148	return 0;
	149	}
	150
	151	#if defined(CONFIG_OF_BOARD_SETUP)
	152	void ft_board_setup(void blob, bd_t bd)
	153	{
19580e66 DL	154	ft_cpu_setup(blob, bd);
	155	#ifdef CONFIG_PCI
	156	ft_pci_setup(blob, bd);
	157	#endif
	158	}
	159	#endif /* CONFIG_OF_BOARD_SETUP */