[people/ms/u-boot.git] / board / freescale / mpc837xerdb / mpc837xerdb.c

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Kevin Lam <kevin.lam@freescale.com>
 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <vsc7385.h>

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);

phys_size_t initdram(int board_type)
{
	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* return total bus DDR size(bytes) */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
	u32 msize_log2 = __ilog2(msize);

	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);

	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
	udelay(50000);

	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
	udelay(1000);

	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	udelay(1000);

	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	sync();
	udelay(1000);

	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	udelay(2000);
	return CONFIG_SYS_DDR_SIZE;
}
#endif	/*!CONFIG_SYS_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC837xERDB\n");
	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_FSL_SERDES
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	u32 spridr = in_be32(&immr->sysconf.spridr);

	/* we check only part num, and don't look for CPU revisions */
	switch (PARTID_NO_E(spridr)) {
	case SPR_8377:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	case SPR_8378:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	case SPR_8379:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	default:
		printf("serdes not configured: unknown CPU part number: "
		       "%04x\n", spridr >> 16);
		break;
	}
#endif /* CONFIG_FSL_SERDES */
	return 0;
}

/*
 * Miscellaneous late-boot configurations
 *
 * If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
	int rc = 0;

#ifdef CONFIG_VSC7385_IMAGE
	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
		CONFIG_VSC7385_IMAGE_SIZE)) {
		puts("Failure uploading VSC7385 microcode.\n");
		rc = 1;
	}
#endif

	return rc;
}

#if defined(CONFIG_OF_BOARD_SETUP)

void ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	ft_cpu_setup(blob, bd);
	fdt_fixup_dr_usb(blob, bd);
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
5e918a98 KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	* Kevin Lam <kevin.lam@freescale.com>
	4	* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*/
	14
	15	#include <common.h>
	16	#include <i2c.h>
5e918a98	17	#include <asm/io.h>
2bd7460e	18	#include <asm/fsl_serdes.h>
1ac4f320	19	#include <fdt_support.h>
5e918a98	20	#include <spd_sdram.h>
89c7784e TT	21	#include <vsc7385.h>
89c7784e TT	22
6d0f6bcf	23	#if defined(CONFIG_SYS_DRAM_TEST)
5e918a98 KP	24	int
	25	testdram(void)
	26	{
6d0f6bcf JCPV	27	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	28	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
5e918a98 KP	29	uint *p;
	30
	31	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	32	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	33	CONFIG_SYS_MEMTEST_END);
5e918a98 KP	34
	35	printf("DRAM test phase 1:\n");
	36	for (p = pstart; p < pend; p++)
	37	*p = 0xaaaaaaaa;
	38
	39	for (p = pstart; p < pend; p++) {
	40	if (*p != 0xaaaaaaaa) {
	41	printf("DRAM test fails at: %08x\n", (uint) p);
	42	return 1;
	43	}
	44	}
	45
	46	printf("DRAM test phase 2:\n");
	47	for (p = pstart; p < pend; p++)
	48	*p = 0x55555555;
	49
	50	for (p = pstart; p < pend; p++) {
	51	if (*p != 0x55555555) {
	52	printf("DRAM test fails at: %08x\n", (uint) p);
	53	return 1;
	54	}
	55	}
	56
	57	printf("DRAM test passed.\n");
	58	return 0;
	59	}
	60	#endif
	61
5e918a98 KP	62	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	63	void ddr_enable_ecc(unsigned int dram_size);
	64	#endif
	65	int fixed_sdram(void);
	66
9973e3c6	67	phys_size_t initdram(int board_type)
5e918a98	68	{
6d0f6bcf	69	immap_t im = (immap_t ) CONFIG_SYS_IMMR;
5e918a98 KP	70	u32 msize = 0;
	71
	72	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	73	return -1;
	74
	75	#if defined(CONFIG_SPD_EEPROM)
	76	msize = spd_sdram();
	77	#else
	78	msize = fixed_sdram();
	79	#endif
	80
	81	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	82	/* Initialize DDR ECC byte */
	83	ddr_enable_ecc(msize * 1024 * 1024);
	84	#endif
	85	/* return total bus DDR size(bytes) */
	86	return (msize * 1024 * 1024);
	87	}
	88
	89	#if !defined(CONFIG_SPD_EEPROM)
	90	/*************************************************************************
	91	* fixed sdram init -- doesn't use serial presence detect.
	92	************************************************************************/
	93	int fixed_sdram(void)
	94	{
6d0f6bcf JCPV	95	immap_t im = (immap_t ) CONFIG_SYS_IMMR;
6d0f6bcf JCPV	96	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
5e918a98 KP	97	u32 msize_log2 = __ilog2(msize);
5e918a98 KP	98
6d0f6bcf	99	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
5e918a98 KP	100	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN \| (msize_log2 - 1);
5e918a98 KP	101
6d0f6bcf	102	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
5e918a98 KP	103	udelay(50000);
5e918a98 KP	104
6d0f6bcf	105	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
5e918a98 KP	106	udelay(1000);
5e918a98 KP	107
6d0f6bcf JCPV	108	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	109	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
5e918a98 KP	110	udelay(1000);
5e918a98 KP	111
6d0f6bcf JCPV	112	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	113	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	114	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	115	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	116	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	117	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	118	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	119	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	120	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
5e918a98 KP	121	sync();
	122	udelay(1000);
	123
	124	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	125	udelay(2000);
6d0f6bcf	126	return CONFIG_SYS_DDR_SIZE;
5e918a98	127	}
6d0f6bcf	128	#endif /!CONFIG_SYS_SPD_EEPROM /
5e918a98 KP	129
	130	int checkboard(void)
	131	{
	132	puts("Board: Freescale MPC837xERDB\n");
	133	return 0;
	134	}
	135
2bd7460e AV	136	int board_early_init_f(void)
	137	{
	138	#ifdef CONFIG_FSL_SERDES
6d0f6bcf	139	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
2bd7460e AV	140	u32 spridr = in_be32(&immr->sysconf.spridr);
	141
	142	/* we check only part num, and don't look for CPU revisions */
e5c4ade4 KP	143	switch (PARTID_NO_E(spridr)) {
e5c4ade4 KP	144	case SPR_8377:
2bd7460e AV	145	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
2bd7460e AV	146	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
e5c4ade4	147	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
2bd7460e AV	148	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
2bd7460e AV	149	break;
e5c4ade4	150	case SPR_8378:
2bd7460e AV	151	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
	152	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	153	break;
e5c4ade4	154	case SPR_8379:
2bd7460e AV	155	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
2bd7460e AV	156	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
e5c4ade4	157	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
2bd7460e AV	158	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	159	break;
	160	default:
	161	printf("serdes not configured: unknown CPU part number: "
	162	"%04x\n", spridr >> 16);
	163	break;
	164	}
	165	#endif /* CONFIG_FSL_SERDES */
	166	return 0;
	167	}
	168
89c7784e TT	169	/*
	170	* Miscellaneous late-boot configurations
	171	*
	172	* If a VSC7385 microcode image is present, then upload it.
	173	*/
	174	int misc_init_r(void)
	175	{
	176	int rc = 0;
	177
	178	#ifdef CONFIG_VSC7385_IMAGE
	179	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
	180	CONFIG_VSC7385_IMAGE_SIZE)) {
	181	puts("Failure uploading VSC7385 microcode.\n");
	182	rc = 1;
	183	}
	184	#endif
	185
	186	return rc;
	187	}
	188
5e918a98 KP	189	#if defined(CONFIG_OF_BOARD_SETUP)
	190
	191	void ft_board_setup(void blob, bd_t bd)
	192	{
	193	#ifdef CONFIG_PCI
	194	ft_pci_setup(blob, bd);
	195	#endif
	196	ft_cpu_setup(blob, bd);
18e69a35	197	fdt_fixup_dr_usb(blob, bd);
5e918a98 KP	198	}
5e918a98 KP	199	#endif /* CONFIG_OF_BOARD_SETUP */