[people/ms/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

/*
 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/sgmii_riser.h"

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	if (vboot & PIXIS_VBOOT_FMAP)
		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	else
		puts ("Promjet\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;

	puts("    DDR: ");
	return dram_size;
}

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info[4];
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno = 0;
	int num = 0;

	int pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

	puts("\n");

#ifdef CONFIG_PCIE3
	pcie_configured = is_serdes_configured(PCIE3);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
		SET_STD_PCIE_INFO(pci_info[num], 3);
		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
		/* outbound memory */
		pci_set_region(&pcie3_hose.regions[0],
			       CONFIG_SYS_PCIE3_MEM_BUS2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie3_hose.region_count = 1;
#endif
		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie3_hose, first_free_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
	} else {
		printf("PCIE3: disabled\n");
	}
	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif

#ifdef CONFIG_PCIE1
	pcie_configured = is_serdes_configured(PCIE1);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		SET_STD_PCIE_INFO(pci_info[num], 1);
		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
		/* outbound memory */
		pci_set_region(&pcie1_hose.regions[0],
			       CONFIG_SYS_PCIE1_MEM_BUS2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie1_hose.region_count = 1;
#endif
		printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
				pcie_ep ? "Endpoint" : "Root Complex",
				pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie1_hose, first_free_busno);
	} else {
		printf("PCIE1: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif

#ifdef CONFIG_PCIE2
	pcie_configured = is_serdes_configured(PCIE2);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
		SET_STD_PCIE_INFO(pci_info[num], 2);
		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
		/* outbound memory */
		pci_set_region(&pcie2_hose.regions[0],
			       CONFIG_SYS_PCIE2_MEM_BUS2,
			       CONFIG_SYS_PCIE2_MEM_PHYS2,
			       CONFIG_SYS_PCIE2_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie2_hose.region_count = 1;
#endif
		printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie2_hose, first_free_busno);
	} else {
		printf("PCIE2: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif

#ifdef CONFIG_PCI1
	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info[num], 1);
		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}


int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	go_bit = in_8(pixis_base + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in_8(pixis_base + PIXIS_AUX);
		else
			i = in_8(pixis_base + PIXIS_SPD);
	} else {
		i = in_8(pixis_base + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct tsec_info_struct tsec_info[2];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (is_serdes_configured(SGMII_TSEC1)) {
		puts("eTSEC1 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	if (is_serdes_configured(SGMII_TSEC1) ||
	    is_serdes_configured(SGMII_TSEC3)) {
		fsl_sgmii_riser_init(tsec_info, num);
	}


	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif
Commit	Line	Data
25d83d7f	1	/*
6525d51f	2	* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
25d83d7f JL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
837f1ba0	25	#include <pci.h>
25d83d7f	26	#include <asm/processor.h>
1167a2fd	27	#include <asm/mmu.h>
25d83d7f	28	#include <asm/immap_85xx.h>
c8514622	29	#include <asm/fsl_pci.h>
1167a2fd	30	#include <asm/fsl_ddr_sdram.h>
5d27e02c	31	#include <asm/fsl_serdes.h>
56a92705	32	#include <asm/io.h>
25d83d7f	33	#include <miiphy.h>
addce57e KG	34	#include <libfdt.h>
addce57e KG	35	#include <fdt_support.h>
216f2a71	36	#include <tsec.h>
0b252f50	37	#include <netdev.h>
25d83d7f	38
216f2a71	39	#include "../common/sgmii_riser.h"
25d83d7f	40
25d83d7f JL	41	int checkboard (void)
25d83d7f JL	42	{
6d0f6bcf	43	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	44	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	45	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6bb5b412 KG	46	u8 vboot;
6bb5b412 KG	47	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	48
2f15278c	49	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	50	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
25d83d7f	51	}
6bb5b412 KG	52	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
	53	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	54	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	55	in_8(pixis_base + PIXIS_PVER));
	56
	57	vboot = in_8(pixis_base + PIXIS_VBOOT);
	58	if (vboot & PIXIS_VBOOT_FMAP)
	59	printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	60	else
	61	puts ("Promjet\n");
25d83d7f	62
837f1ba0 ES	63	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	64	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	65	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	66	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	67
25d83d7f JL	68	return 0;
	69	}
	70
9973e3c6	71	phys_size_t
25d83d7f JL	72	initdram(int board_type)
	73	{
	74	long dram_size = 0;
	75
	76	puts("Initializing\n");
	77
1167a2fd KG	78	dram_size = fsl_ddr_sdram();
	79
	80	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	81
	82	dram_size *= 0x100000;
25d83d7f	83
25d83d7f JL	84	puts(" DDR: ");
	85	return dram_size;
	86	}
	87
837f1ba0 ES	88	#ifdef CONFIG_PCI1
	89	static struct pci_controller pci1_hose;
	90	#endif
	91
	92	#ifdef CONFIG_PCIE1
	93	static struct pci_controller pcie1_hose;
	94	#endif
	95
	96	#ifdef CONFIG_PCIE2
	97	static struct pci_controller pcie2_hose;
	98	#endif
	99
	100	#ifdef CONFIG_PCIE3
	101	static struct pci_controller pcie3_hose;
	102	#endif
	103
645d5a78	104	void pci_init_board(void)
837f1ba0	105	{
6d0f6bcf	106	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
645d5a78 KG	107	struct fsl_pci_info pci_info[4];
	108	u32 devdisr, pordevsr, io_sel;
	109	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	110	int first_free_busno = 0;
	111	int num = 0;
	112
	113	int pcie_ep, pcie_configured;
837f1ba0	114
645d5a78 KG	115	devdisr = in_be32(&gur->devdisr);
	116	pordevsr = in_be32(&gur->pordevsr);
	117	porpllsr = in_be32(&gur->porpllsr);
	118	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	119
	120	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
837f1ba0	121
645d5a78	122	puts("\n");
837f1ba0 ES	123
837f1ba0 ES	124	#ifdef CONFIG_PCIE3
5d27e02c	125	pcie_configured = is_serdes_configured(PCIE3);
837f1ba0	126
645d5a78 KG	127	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
	128	SET_STD_PCIE_INFO(pci_info[num], 3);
	129	pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
10795f42	130	#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
837f1ba0	131	/* outbound memory */
645d5a78	132	pci_set_region(&pcie3_hose.regions[0],
10795f42	133	CONFIG_SYS_PCIE3_MEM_BUS2,
6d0f6bcf JCPV	134	CONFIG_SYS_PCIE3_MEM_PHYS2,
6d0f6bcf JCPV	135	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	136	PCI_REGION_MEM);
837f1ba0	137
645d5a78 KG	138	pcie3_hose.region_count = 1;
645d5a78 KG	139	#endif
8ca78f2c PT	140	printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
	141	pcie_ep ? "Endpoint" : "Root Complex",
	142	pci_info[num].regs);
645d5a78 KG	143	first_free_busno = fsl_pci_init_port(&pci_info[num++],
645d5a78 KG	144	&pcie3_hose, first_free_busno);
837f1ba0	145
56a92705 KG	146	/*
	147	* Activate ULI1575 legacy chip by performing a fake
	148	* memory access. Needed to make ULI RTC work.
	149	*/
10795f42	150	in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
837f1ba0	151	} else {
8ca78f2c	152	printf("PCIE3: disabled\n");
837f1ba0	153	}
645d5a78	154	puts("\n");
837f1ba0	155	#else
645d5a78	156	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
837f1ba0 ES	157	#endif
	158
	159	#ifdef CONFIG_PCIE1
5d27e02c	160	pcie_configured = is_serdes_configured(PCIE1);
837f1ba0 ES	161
837f1ba0 ES	162	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
645d5a78 KG	163	SET_STD_PCIE_INFO(pci_info[num], 1);
645d5a78 KG	164	pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
10795f42	165	#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
837f1ba0	166	/* outbound memory */
645d5a78	167	pci_set_region(&pcie1_hose.regions[0],
10795f42	168	CONFIG_SYS_PCIE1_MEM_BUS2,
6d0f6bcf JCPV	169	CONFIG_SYS_PCIE1_MEM_PHYS2,
6d0f6bcf JCPV	170	CONFIG_SYS_PCIE1_MEM_SIZE2,
837f1ba0	171	PCI_REGION_MEM);
837f1ba0	172
645d5a78 KG	173	pcie1_hose.region_count = 1;
645d5a78 KG	174	#endif
8ca78f2c	175	printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
64917ca3	176	pcie_ep ? "Endpoint" : "Root Complex",
645d5a78	177	pci_info[num].regs);
837f1ba0	178
645d5a78 KG	179	first_free_busno = fsl_pci_init_port(&pci_info[num++],
645d5a78 KG	180	&pcie1_hose, first_free_busno);
837f1ba0	181	} else {
8ca78f2c	182	printf("PCIE1: disabled\n");
837f1ba0 ES	183	}
837f1ba0 ES	184
645d5a78	185	puts("\n");
837f1ba0	186	#else
645d5a78	187	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
837f1ba0 ES	188	#endif
	189
	190	#ifdef CONFIG_PCIE2
5d27e02c	191	pcie_configured = is_serdes_configured(PCIE2);
837f1ba0	192
645d5a78 KG	193	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
	194	SET_STD_PCIE_INFO(pci_info[num], 2);
	195	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
10795f42	196	#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
837f1ba0	197	/* outbound memory */
645d5a78	198	pci_set_region(&pcie2_hose.regions[0],
10795f42	199	CONFIG_SYS_PCIE2_MEM_BUS2,
6d0f6bcf JCPV	200	CONFIG_SYS_PCIE2_MEM_PHYS2,
6d0f6bcf JCPV	201	CONFIG_SYS_PCIE2_MEM_SIZE2,
837f1ba0	202	PCI_REGION_MEM);
837f1ba0	203
645d5a78 KG	204	pcie2_hose.region_count = 1;
645d5a78 KG	205	#endif
8ca78f2c PT	206	printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
	207	pcie_ep ? "Endpoint" : "Root Complex",
	208	pci_info[num].regs);
645d5a78 KG	209	first_free_busno = fsl_pci_init_port(&pci_info[num++],
645d5a78 KG	210	&pcie2_hose, first_free_busno);
837f1ba0	211	} else {
8ca78f2c	212	printf("PCIE2: disabled\n");
837f1ba0 ES	213	}
837f1ba0 ES	214
645d5a78	215	puts("\n");
837f1ba0	216	#else
645d5a78	217	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
837f1ba0 ES	218	#endif
837f1ba0 ES	219
837f1ba0	220	#ifdef CONFIG_PCI1
645d5a78 KG	221	pci_speed = 66666000;
	222	pci_32 = 1;
	223	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	224	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
837f1ba0 ES	225
837f1ba0 ES	226	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
645d5a78 KG	227	SET_STD_PCI_INFO(pci_info[num], 1);
645d5a78 KG	228	pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
8ca78f2c	229	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
837f1ba0 ES	230	(pci_32) ? 32 : 64,
	231	(pci_speed == 33333000) ? "33" :
	232	(pci_speed == 66666000) ? "66" : "unknown",
	233	pci_clk_sel ? "sync" : "async",
	234	pci_agent ? "agent" : "host",
	235	pci_arb ? "arbiter" : "external-arbiter",
645d5a78	236	pci_info[num].regs);
837f1ba0	237
645d5a78 KG	238	first_free_busno = fsl_pci_init_port(&pci_info[num++],
645d5a78 KG	239	&pci1_hose, first_free_busno);
837f1ba0	240	} else {
8ca78f2c	241	printf("PCI: disabled\n");
837f1ba0	242	}
645d5a78 KG	243
645d5a78 KG	244	puts("\n");
837f1ba0	245	#else
645d5a78	246	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
837f1ba0 ES	247	#endif
	248	}
	249
	250
25d83d7f JL	251	int last_stage_init(void)
	252	{
	253	return 0;
	254	}
	255
	256
	257	unsigned long
	258	get_board_sys_clk(ulong dummy)
	259	{
	260	u8 i, go_bit, rd_clks;
	261	ulong val = 0;
048e7efe	262	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	263
048e7efe	264	go_bit = in_8(pixis_base + PIXIS_VCTL);
25d83d7f JL	265	go_bit &= 0x01;
25d83d7f JL	266
048e7efe	267	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
25d83d7f JL	268	rd_clks &= 0x1C;
	269
	270	/*
	271	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	272	* should we be using the AUX register. Remember, we also set the
	273	* GO bit to boot from the alternate bank on the on-board flash
	274	*/
	275
	276	if (go_bit) {
	277	if (rd_clks == 0x1c)
048e7efe	278	i = in_8(pixis_base + PIXIS_AUX);
25d83d7f	279	else
048e7efe	280	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f	281	} else {
048e7efe	282	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f JL	283	}
	284
	285	i &= 0x07;
	286
	287	switch (i) {
	288	case 0:
	289	val = 33333333;
	290	break;
	291	case 1:
	292	val = 40000000;
	293	break;
	294	case 2:
	295	val = 50000000;
	296	break;
	297	case 3:
	298	val = 66666666;
	299	break;
	300	case 4:
	301	val = 83000000;
	302	break;
	303	case 5:
	304	val = 100000000;
	305	break;
	306	case 6:
	307	val = 133333333;
	308	break;
	309	case 7:
	310	val = 166666666;
	311	break;
	312	}
	313
	314	return val;
	315	}
	316
216f2a71 AF	317	int board_eth_init(bd_t *bis)
216f2a71 AF	318	{
0b252f50	319	#ifdef CONFIG_TSEC_ENET
216f2a71	320	struct tsec_info_struct tsec_info[2];
216f2a71 AF	321	int num = 0;
	322
	323	#ifdef CONFIG_TSEC1
	324	SET_STD_TSEC_INFO(tsec_info[num], 1);
058d7dc7 KG	325	if (is_serdes_configured(SGMII_TSEC1)) {
058d7dc7 KG	326	puts("eTSEC1 is in sgmii mode.\n");
216f2a71	327	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	328	}
216f2a71 AF	329	num++;
	330	#endif
	331	#ifdef CONFIG_TSEC3
	332	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	333	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	334	puts("eTSEC3 is in sgmii mode.\n");
216f2a71	335	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	336	}
216f2a71 AF	337	num++;
	338	#endif
	339
	340	if (!num) {
	341	printf("No TSECs initialized\n");
	342
	343	return 0;
	344	}
	345
058d7dc7 KG	346	if (is_serdes_configured(SGMII_TSEC1) \|\|
058d7dc7 KG	347	is_serdes_configured(SGMII_TSEC3)) {
216f2a71	348	fsl_sgmii_riser_init(tsec_info, num);
058d7dc7	349	}
216f2a71 AF	350
	351
	352	tsec_eth_init(bis, tsec_info, num);
216f2a71	353	#endif
0b252f50 BW	354	return pci_eth_init(bis);
0b252f50 BW	355	}
216f2a71	356
addce57e	357	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	358	void ft_board_setup(void blob, bd_t bd)
25d83d7f	359	{
2f15278c	360	ft_cpu_setup(blob, bd);
25d83d7f	361
6525d51f	362	FT_FSL_PCI_SETUP;
2dba0dea	363
feede8b0 AF	364	#ifdef CONFIG_FSL_SGMII_RISER
	365	fsl_sgmii_riser_fdt_fixup(blob);
	366	#endif
25d83d7f JL	367	}
25d83d7f JL	368	#endif