[people/ms/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

/*
 * Copyright 2007,2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/sgmii_riser.h"

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	if (vboot & PIXIS_VBOOT_FMAP)
		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	else
		puts ("Promjet\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;

	puts("    DDR: ");
	return dram_size;
}

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info[4];
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno = 0;
	int num = 0;

	int pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

	if (io_sel & 1) {
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
			printf ("    eTSEC1 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
			printf ("    eTSEC3 is in sgmii mode.\n");
	}
	puts("\n");

#ifdef CONFIG_PCIE3
	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
		SET_STD_PCIE_INFO(pci_info[num], 3);
		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
		/* outbound memory */
		pci_set_region(&pcie3_hose.regions[0],
			       CONFIG_SYS_PCIE3_MEM_BUS2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie3_hose.region_count = 1;
#endif
		printf ("    PCIE3 connected to ULI as %s (base addr %lx)\n",
				pcie_ep ? "Endpoint" : "Root Complex",
				pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie3_hose, first_free_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
	} else {
		printf ("    PCIE3: disabled\n");
	}
	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif

#ifdef CONFIG_PCIE1
	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		SET_STD_PCIE_INFO(pci_info[num], 1);
		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
		/* outbound memory */
		pci_set_region(&pcie1_hose.regions[0],
			       CONFIG_SYS_PCIE1_MEM_BUS2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie1_hose.region_count = 1;
#endif
		printf ("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
				pcie_ep ? "Endpoint" : "Root Complex",
				pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie1_hose, first_free_busno);
	} else {
		printf ("    PCIE1: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif

#ifdef CONFIG_PCIE2
	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
		SET_STD_PCIE_INFO(pci_info[num], 2);
		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
		/* outbound memory */
		pci_set_region(&pcie2_hose.regions[0],
			       CONFIG_SYS_PCIE2_MEM_BUS2,
			       CONFIG_SYS_PCIE2_MEM_PHYS2,
			       CONFIG_SYS_PCIE2_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie2_hose.region_count = 1;
#endif
		printf ("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
				pcie_ep ? "Endpoint" : "Root Complex",
				pci_info[num].regs);
		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie2_hose, first_free_busno);
	} else {
		printf ("    PCIE2: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif

#ifdef CONFIG_PCI1
	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info[num], 1);
		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pci1_hose, first_free_busno);
	} else {
		printf ("    PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}


int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	go_bit = in_8(pixis_base + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in_8(pixis_base + PIXIS_AUX);
		else
			i = in_8(pixis_base + PIXIS_SPD);
	} else {
		i = in_8(pixis_base + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct tsec_info_struct tsec_info[2];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	if (io_sel & 1)
		fsl_sgmii_riser_init(tsec_info, num);


	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);


#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE3
	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif
Commit	Line	Data
25d83d7f	1	/*
645d5a78	2	* Copyright 2007,2009 Freescale Semiconductor, Inc.
25d83d7f JL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
837f1ba0	25	#include <pci.h>
25d83d7f	26	#include <asm/processor.h>
1167a2fd	27	#include <asm/mmu.h>
25d83d7f	28	#include <asm/immap_85xx.h>
c8514622	29	#include <asm/fsl_pci.h>
1167a2fd	30	#include <asm/fsl_ddr_sdram.h>
56a92705	31	#include <asm/io.h>
25d83d7f	32	#include <miiphy.h>
addce57e KG	33	#include <libfdt.h>
addce57e KG	34	#include <fdt_support.h>
216f2a71	35	#include <tsec.h>
0b252f50	36	#include <netdev.h>
25d83d7f	37
216f2a71	38	#include "../common/sgmii_riser.h"
25d83d7f	39
25d83d7f JL	40	int checkboard (void)
25d83d7f JL	41	{
6d0f6bcf JCPV	42	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	43	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	44	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6bb5b412 KG	45	u8 vboot;
6bb5b412 KG	46	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	47
2f15278c	48	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	49	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
25d83d7f	50	}
6bb5b412 KG	51	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
	52	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	53	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	54	in_8(pixis_base + PIXIS_PVER));
	55
	56	vboot = in_8(pixis_base + PIXIS_VBOOT);
	57	if (vboot & PIXIS_VBOOT_FMAP)
	58	printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	59	else
	60	puts ("Promjet\n");
25d83d7f	61
837f1ba0 ES	62	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	63	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	64	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	65	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	66
25d83d7f JL	67	return 0;
	68	}
	69
9973e3c6	70	phys_size_t
25d83d7f JL	71	initdram(int board_type)
	72	{
	73	long dram_size = 0;
	74
	75	puts("Initializing\n");
	76
1167a2fd KG	77	dram_size = fsl_ddr_sdram();
	78
	79	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	80
	81	dram_size *= 0x100000;
25d83d7f	82
25d83d7f JL	83	puts(" DDR: ");
	84	return dram_size;
	85	}
	86
837f1ba0 ES	87	#ifdef CONFIG_PCI1
	88	static struct pci_controller pci1_hose;
	89	#endif
	90
	91	#ifdef CONFIG_PCIE1
	92	static struct pci_controller pcie1_hose;
	93	#endif
	94
	95	#ifdef CONFIG_PCIE2
	96	static struct pci_controller pcie2_hose;
	97	#endif
	98
	99	#ifdef CONFIG_PCIE3
	100	static struct pci_controller pcie3_hose;
	101	#endif
	102
645d5a78	103	void pci_init_board(void)
837f1ba0	104	{
6d0f6bcf	105	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
645d5a78 KG	106	struct fsl_pci_info pci_info[4];
	107	u32 devdisr, pordevsr, io_sel;
	108	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	109	int first_free_busno = 0;
	110	int num = 0;
	111
	112	int pcie_ep, pcie_configured;
837f1ba0	113
645d5a78 KG	114	devdisr = in_be32(&gur->devdisr);
	115	pordevsr = in_be32(&gur->pordevsr);
	116	porpllsr = in_be32(&gur->porpllsr);
	117	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	118
	119	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
837f1ba0 ES	120
	121	if (io_sel & 1) {
	122	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	123	printf (" eTSEC1 is in sgmii mode.\n");
	124	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	125	printf (" eTSEC3 is in sgmii mode.\n");
	126	}
645d5a78	127	puts("\n");
837f1ba0 ES	128
837f1ba0 ES	129	#ifdef CONFIG_PCIE3
645d5a78	130	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
837f1ba0	131
645d5a78 KG	132	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
	133	SET_STD_PCIE_INFO(pci_info[num], 3);
	134	pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
10795f42	135	#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
837f1ba0	136	/* outbound memory */
645d5a78	137	pci_set_region(&pcie3_hose.regions[0],
10795f42	138	CONFIG_SYS_PCIE3_MEM_BUS2,
6d0f6bcf JCPV	139	CONFIG_SYS_PCIE3_MEM_PHYS2,
6d0f6bcf JCPV	140	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	141	PCI_REGION_MEM);
837f1ba0	142
645d5a78 KG	143	pcie3_hose.region_count = 1;
	144	#endif
	145	printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
64917ca3	146	pcie_ep ? "Endpoint" : "Root Complex",
645d5a78 KG	147	pci_info[num].regs);
	148	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	149	&pcie3_hose, first_free_busno);
837f1ba0	150
56a92705 KG	151	/*
	152	* Activate ULI1575 legacy chip by performing a fake
	153	* memory access. Needed to make ULI RTC work.
	154	*/
10795f42	155	in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
837f1ba0 ES	156	} else {
	157	printf (" PCIE3: disabled\n");
	158	}
645d5a78	159	puts("\n");
837f1ba0	160	#else
645d5a78	161	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
837f1ba0 ES	162	#endif
	163
	164	#ifdef CONFIG_PCIE1
645d5a78	165	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
837f1ba0 ES	166
837f1ba0 ES	167	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
645d5a78 KG	168	SET_STD_PCIE_INFO(pci_info[num], 1);
645d5a78 KG	169	pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
10795f42	170	#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
837f1ba0	171	/* outbound memory */
645d5a78	172	pci_set_region(&pcie1_hose.regions[0],
10795f42	173	CONFIG_SYS_PCIE1_MEM_BUS2,
6d0f6bcf JCPV	174	CONFIG_SYS_PCIE1_MEM_PHYS2,
6d0f6bcf JCPV	175	CONFIG_SYS_PCIE1_MEM_SIZE2,
837f1ba0	176	PCI_REGION_MEM);
837f1ba0	177
645d5a78 KG	178	pcie1_hose.region_count = 1;
	179	#endif
	180	printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
64917ca3	181	pcie_ep ? "Endpoint" : "Root Complex",
645d5a78	182	pci_info[num].regs);
837f1ba0	183
645d5a78 KG	184	first_free_busno = fsl_pci_init_port(&pci_info[num++],
645d5a78 KG	185	&pcie1_hose, first_free_busno);
837f1ba0 ES	186	} else {
	187	printf (" PCIE1: disabled\n");
	188	}
	189
645d5a78	190	puts("\n");
837f1ba0	191	#else
645d5a78	192	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
837f1ba0 ES	193	#endif
	194
	195	#ifdef CONFIG_PCIE2
645d5a78	196	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
837f1ba0	197
645d5a78 KG	198	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
	199	SET_STD_PCIE_INFO(pci_info[num], 2);
	200	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
10795f42	201	#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
837f1ba0	202	/* outbound memory */
645d5a78	203	pci_set_region(&pcie2_hose.regions[0],
10795f42	204	CONFIG_SYS_PCIE2_MEM_BUS2,
6d0f6bcf JCPV	205	CONFIG_SYS_PCIE2_MEM_PHYS2,
6d0f6bcf JCPV	206	CONFIG_SYS_PCIE2_MEM_SIZE2,
837f1ba0	207	PCI_REGION_MEM);
837f1ba0	208
645d5a78 KG	209	pcie2_hose.region_count = 1;
	210	#endif
	211	printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
64917ca3	212	pcie_ep ? "Endpoint" : "Root Complex",
645d5a78 KG	213	pci_info[num].regs);
	214	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	215	&pcie2_hose, first_free_busno);
837f1ba0 ES	216	} else {
	217	printf (" PCIE2: disabled\n");
	218	}
	219
645d5a78	220	puts("\n");
837f1ba0	221	#else
645d5a78	222	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
837f1ba0 ES	223	#endif
837f1ba0 ES	224
837f1ba0	225	#ifdef CONFIG_PCI1
645d5a78 KG	226	pci_speed = 66666000;
	227	pci_32 = 1;
	228	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	229	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
837f1ba0 ES	230
837f1ba0 ES	231	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
645d5a78 KG	232	SET_STD_PCI_INFO(pci_info[num], 1);
	233	pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
	234	printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
837f1ba0 ES	235	(pci_32) ? 32 : 64,
	236	(pci_speed == 33333000) ? "33" :
	237	(pci_speed == 66666000) ? "66" : "unknown",
	238	pci_clk_sel ? "sync" : "async",
	239	pci_agent ? "agent" : "host",
	240	pci_arb ? "arbiter" : "external-arbiter",
645d5a78	241	pci_info[num].regs);
837f1ba0	242
645d5a78 KG	243	first_free_busno = fsl_pci_init_port(&pci_info[num++],
645d5a78 KG	244	&pci1_hose, first_free_busno);
837f1ba0 ES	245	} else {
	246	printf (" PCI: disabled\n");
	247	}
645d5a78 KG	248
645d5a78 KG	249	puts("\n");
837f1ba0	250	#else
645d5a78	251	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
837f1ba0 ES	252	#endif
	253	}
	254
	255
25d83d7f JL	256	int last_stage_init(void)
	257	{
	258	return 0;
	259	}
	260
	261
	262	unsigned long
	263	get_board_sys_clk(ulong dummy)
	264	{
	265	u8 i, go_bit, rd_clks;
	266	ulong val = 0;
048e7efe	267	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	268
048e7efe	269	go_bit = in_8(pixis_base + PIXIS_VCTL);
25d83d7f JL	270	go_bit &= 0x01;
25d83d7f JL	271
048e7efe	272	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
25d83d7f JL	273	rd_clks &= 0x1C;
	274
	275	/*
	276	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	277	* should we be using the AUX register. Remember, we also set the
	278	* GO bit to boot from the alternate bank on the on-board flash
	279	*/
	280
	281	if (go_bit) {
	282	if (rd_clks == 0x1c)
048e7efe	283	i = in_8(pixis_base + PIXIS_AUX);
25d83d7f	284	else
048e7efe	285	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f	286	} else {
048e7efe	287	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f JL	288	}
	289
	290	i &= 0x07;
	291
	292	switch (i) {
	293	case 0:
	294	val = 33333333;
	295	break;
	296	case 1:
	297	val = 40000000;
	298	break;
	299	case 2:
	300	val = 50000000;
	301	break;
	302	case 3:
	303	val = 66666666;
	304	break;
	305	case 4:
	306	val = 83000000;
	307	break;
	308	case 5:
	309	val = 100000000;
	310	break;
	311	case 6:
	312	val = 133333333;
	313	break;
	314	case 7:
	315	val = 166666666;
	316	break;
	317	}
	318
	319	return val;
	320	}
	321
216f2a71 AF	322	int board_eth_init(bd_t *bis)
216f2a71 AF	323	{
0b252f50	324	#ifdef CONFIG_TSEC_ENET
216f2a71	325	struct tsec_info_struct tsec_info[2];
6d0f6bcf	326	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
216f2a71 AF	327	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	328	int num = 0;
	329
	330	#ifdef CONFIG_TSEC1
	331	SET_STD_TSEC_INFO(tsec_info[num], 1);
	332	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	333	tsec_info[num].flags \|= TSEC_SGMII;
	334	num++;
	335	#endif
	336	#ifdef CONFIG_TSEC3
	337	SET_STD_TSEC_INFO(tsec_info[num], 3);
	338	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	339	tsec_info[num].flags \|= TSEC_SGMII;
	340	num++;
	341	#endif
	342
	343	if (!num) {
	344	printf("No TSECs initialized\n");
	345
	346	return 0;
	347	}
	348
	349	if (io_sel & 1)
	350	fsl_sgmii_riser_init(tsec_info, num);
	351
	352
	353	tsec_eth_init(bis, tsec_info, num);
216f2a71	354	#endif
0b252f50 BW	355	return pci_eth_init(bis);
0b252f50 BW	356	}
216f2a71	357
addce57e	358	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	359	void ft_board_setup(void blob, bd_t bd)
25d83d7f	360	{
2f15278c	361	ft_cpu_setup(blob, bd);
25d83d7f	362
2dba0dea	363
f75e89e9	364	#ifdef CONFIG_PCI1
2dba0dea	365	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
837f1ba0 ES	366	#endif
837f1ba0 ES	367	#ifdef CONFIG_PCIE2
2dba0dea	368	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
addce57e KG	369	#endif
addce57e KG	370	#ifdef CONFIG_PCIE1
2dba0dea	371	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
837f1ba0 ES	372	#endif
837f1ba0 ES	373	#ifdef CONFIG_PCIE3
2dba0dea	374	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
837f1ba0	375	#endif
feede8b0 AF	376	#ifdef CONFIG_FSL_SGMII_RISER
	377	fsl_sgmii_riser_fdt_fixup(blob);
	378	#endif
25d83d7f JL	379	}
25d83d7f JL	380	#endif