[people/ms/u-boot.git] / board / freescale / mpc8548cds / mpc8548cds.c

/*
 * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

#include "../common/cadmus.h"
#include "../common/eeprom.h"
#include "../common/via.h"

DECLARE_GLOBAL_DATA_PTR;

void local_bus_init(void);
void sdram_init(void);

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);

	/* PCI slot in USER bits CSR[6:7] by convention. */
	uint pci_slot = get_pci_slot ();

	uint cpu_board_rev = get_cpu_board_revision ();

	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
		get_board_version (), pci_slot);

	printf ("CPU Board Revision %d.%d (0x%04x)\n",
		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	/*
	 * Hack TSEC 3 and 4 IO voltages.
	 */
	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */

	ecm->eedr = 0xffffffff;		/* clear ecm errors */
	ecm->eeer = 0xffffffff;		/* enable ecm errors */
	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif

	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)

	uint idx;
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint cpu_board_rev;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
	asm("msync");

	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
	asm("msync");

	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");


	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8548 uses "new" 15-16 style addressing.
	 */
	cpu_board_rev = get_cpu_board_revision();
	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
	lsdmr_common |= LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
 * different device.  Work around that by refusing to configure it.
 */
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }

static struct pci_config_table pci_mpc85xxcds_config_table[] = {
	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
		mpc85xx_config_via_usbide, {0,0,0}},
	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
		mpc85xx_config_via_usb, {0,0,0}},
	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
		mpc85xx_config_via_usb2, {0,0,0}},
	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
		mpc85xx_config_via_power, {0,0,0}},
	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
		mpc85xx_config_via_ac97, {0,0,0}},
	{},
};

static struct pci_controller pci1_hose = {
	config_table: pci_mpc85xxcds_config_table};
#endif	/* CONFIG_PCI */

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif	/* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif	/* CONFIG_PCIE1 */

void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info[4];
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno = 0;
	int num = 0;

	int pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

#ifdef CONFIG_PCI1
	pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info[num], 1);
		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pci1_hose, first_free_busno);

#ifdef CONFIG_PCIX_CHECK
		if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
			/* PCI-X init */
			if (CONFIG_SYS_CLK_FREQ < 66000000)
				printf("PCI-X will only work at 66 MHz\n");

			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
		}
#endif
	} else {
		printf ("    PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

#ifdef CONFIG_PCI2
{
	uint pci2_clk_sel = porpllsr & 0x4000;	/* PORPLLSR[17] */
	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
	if (pci_dual) {
		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
			pci2_clk_sel ? "sync" : "async");
	} else {
		printf ("    PCI2: disabled\n");
	}
}
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
#endif /* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		SET_STD_PCIE_INFO(pci_info[num], 1);
		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
		printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
				pcie_ep ? "Endpoint" : "Root Complex",
				pci_info[num].regs);

		first_free_busno = fsl_pci_init_port(&pci_info[num++],
					&pcie1_hose, first_free_busno);
	} else {
		printf ("    PCIE1: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}

int last_stage_init(void)
{
	unsigned short temp;

	/* Change the resistors for the PHY */
	/* This is needed to get the RGMII working for the 1.3+
	 * CDS cards */
	if (get_board_version() ==  0x13) {
		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 18);

		miiphy_read(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, &temp);

		temp = (temp & 0xf03f);
		temp |= 2 << 9;		/* 36 ohm */
		temp |= 2 << 6;		/* 39 ohm */

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, temp);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 3);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, 0x8000);
	}

	return 0;
}


#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
}
#endif
Commit	Line	Data
d9b94f28	1	/*
7b626880	2	* Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
d9b94f28 JL	3	*
	4	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
e31d2c1e	28	#include <asm/mmu.h>
d9b94f28	29	#include <asm/immap_85xx.h>
c8514622	30	#include <asm/fsl_pci.h>
e31d2c1e	31	#include <asm/fsl_ddr_sdram.h>
a30a549a	32	#include <spd_sdram.h>
09f3e09e	33	#include <miiphy.h>
b90d2549 KG	34	#include <libfdt.h>
b90d2549 KG	35	#include <fdt_support.h>
d9b94f28 JL	36
	37	#include "../common/cadmus.h"
	38	#include "../common/eeprom.h"
bf1dfffd	39	#include "../common/via.h"
d9b94f28	40
f2cff6b1 ES	41	DECLARE_GLOBAL_DATA_PTR;
f2cff6b1 ES	42
d9b94f28 JL	43	void local_bus_init(void);
	44	void sdram_init(void);
	45
d9b94f28 JL	46	int checkboard (void)
d9b94f28 JL	47	{
6d0f6bcf JCPV	48	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
6d0f6bcf JCPV	49	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
d9b94f28 JL	50
	51	/* PCI slot in USER bits CSR[6:7] by convention. */
	52	uint pci_slot = get_pci_slot ();
	53
d9b94f28 JL	54	uint cpu_board_rev = get_cpu_board_revision ();
	55
	56	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
	57	get_board_version (), pci_slot);
	58
	59	printf ("CPU Board Revision %d.%d (0x%04x)\n",
	60	MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
	61	MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
d9b94f28 JL	62	/*
	63	* Initialize local bus.
	64	*/
	65	local_bus_init ();
	66
d9b94f28 JL	67	/*
	68	* Hack TSEC 3 and 4 IO voltages.
	69	*/
	70	gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
	71
f2cff6b1 ES	72	ecm->eedr = 0xffffffff; /* clear ecm errors */
f2cff6b1 ES	73	ecm->eeer = 0xffffffff; /* enable ecm errors */
d9b94f28 JL	74	return 0;
	75	}
	76
9973e3c6	77	phys_size_t
d9b94f28 JL	78	initdram(int board_type)
	79	{
	80	long dram_size = 0;
d9b94f28 JL	81
	82	puts("Initializing\n");
	83
	84	#if defined(CONFIG_DDR_DLL)
	85	{
	86	/*
	87	* Work around to stabilize DDR DLL MSYNC_IN.
	88	* Errata DDR9 seems to have been fixed.
	89	* This is now the workaround for Errata DDR11:
	90	* Override DLL = 1, Course Adj = 1, Tap Select = 0
	91	*/
	92
6d0f6bcf	93	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
d9b94f28 JL	94
	95	gur->ddrdllcr = 0x81000000;
	96	asm("sync;isync;msync");
	97	udelay(200);
	98	}
	99	#endif
e31d2c1e JL	100
	101	dram_size = fsl_ddr_sdram();
	102	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	103	dram_size *= 0x100000;
d9b94f28	104
d9b94f28 JL	105	/*
	106	* SDRAM Initialization
	107	*/
	108	sdram_init();
	109
	110	puts(" DDR: ");
	111	return dram_size;
	112	}
	113
	114	/*
	115	* Initialize Local Bus
	116	*/
	117	void
	118	local_bus_init(void)
	119	{
6d0f6bcf JCPV	120	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
6d0f6bcf JCPV	121	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
d9b94f28 JL	122
	123	uint clkdiv;
	124	uint lbc_hz;
	125	sys_info_t sysinfo;
	126
	127	get_sys_info(&sysinfo);
a5d212a2	128	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
d9b94f28 JL	129	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	130
	131	gur->lbiuiplldcr1 = 0x00078080;
	132	if (clkdiv == 16) {
	133	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	134	} else if (clkdiv == 8) {
	135	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	136	} else if (clkdiv == 4) {
	137	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	138	}
	139
	140	lbc->lcrr \|= 0x00030000;
	141
	142	asm("sync;isync;msync");
f2cff6b1 ES	143
	144	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	145	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
d9b94f28 JL	146	}
	147
	148	/*
	149	* Initialize SDRAM memory on the Local Bus.
	150	*/
	151	void
	152	sdram_init(void)
	153	{
6d0f6bcf	154	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
d9b94f28 JL	155
d9b94f28 JL	156	uint idx;
6d0f6bcf JCPV	157	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
6d0f6bcf JCPV	158	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
d9b94f28 JL	159	uint cpu_board_rev;
	160	uint lsdmr_common;
	161
	162	puts(" SDRAM: ");
	163
6d0f6bcf	164	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
d9b94f28 JL	165
	166	/*
	167	* Setup SDRAM Base and Option Registers
	168	*/
6d0f6bcf	169	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
d9b94f28 JL	170	asm("msync");
d9b94f28 JL	171
6d0f6bcf	172	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
d9b94f28 JL	173	asm("msync");
d9b94f28 JL	174
6d0f6bcf	175	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
d9b94f28 JL	176	asm("msync");
	177
	178
6d0f6bcf JCPV	179	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	180	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
d9b94f28 JL	181	asm("msync");
	182
	183	/*
	184	* MPC8548 uses "new" 15-16 style addressing.
	185	*/
	186	cpu_board_rev = get_cpu_board_revision();
6d0f6bcf	187	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
b0fe93ed	188	lsdmr_common \|= LSDMR_BSMA1516;
d9b94f28 JL	189
	190	/*
	191	* Issue PRECHARGE ALL command.
	192	*/
b0fe93ed	193	lbc->lsdmr = lsdmr_common \| LSDMR_OP_PCHALL;
d9b94f28 JL	194	asm("sync;msync");
	195	*sdram_addr = 0xff;
	196	ppcDcbf((unsigned long) sdram_addr);
	197	udelay(100);
	198
	199	/*
	200	* Issue 8 AUTO REFRESH commands.
	201	*/
	202	for (idx = 0; idx < 8; idx++) {
b0fe93ed	203	lbc->lsdmr = lsdmr_common \| LSDMR_OP_ARFRSH;
d9b94f28 JL	204	asm("sync;msync");
	205	*sdram_addr = 0xff;
	206	ppcDcbf((unsigned long) sdram_addr);
	207	udelay(100);
	208	}
	209
	210	/*
	211	* Issue 8 MODE-set command.
	212	*/
b0fe93ed	213	lbc->lsdmr = lsdmr_common \| LSDMR_OP_MRW;
d9b94f28 JL	214	asm("sync;msync");
	215	*sdram_addr = 0xff;
	216	ppcDcbf((unsigned long) sdram_addr);
	217	udelay(100);
	218
	219	/*
	220	* Issue NORMAL OP command.
	221	*/
b0fe93ed	222	lbc->lsdmr = lsdmr_common \| LSDMR_OP_NORMAL;
d9b94f28 JL	223	asm("sync;msync");
	224	*sdram_addr = 0xff;
	225	ppcDcbf((unsigned long) sdram_addr);
	226	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	227
	228	#endif /* enable SDRAM init */
	229	}
	230
f2cff6b1	231	#if defined(CONFIG_PCI) \|\| defined(CONFIG_PCI1)
bf1dfffd MM	232	/* For some reason the Tundra PCI bridge shows up on itself as a
bf1dfffd MM	233	* different device. Work around that by refusing to configure it.
d9b94f28	234	*/
bf1dfffd	235	void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
d9b94f28	236
d9b94f28	237	static struct pci_config_table pci_mpc85xxcds_config_table[] = {
bf1dfffd	238	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
7f3f2bd2 RV	239	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
7f3f2bd2 RV	240	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
ffa621a0	241	mpc85xx_config_via_usbide, {0,0,0}},
7f3f2bd2 RV	242	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
	243	mpc85xx_config_via_usb, {0,0,0}},
	244	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
	245	mpc85xx_config_via_usb2, {0,0,0}},
	246	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
ffa621a0	247	mpc85xx_config_via_power, {0,0,0}},
7f3f2bd2 RV	248	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
7f3f2bd2 RV	249	mpc85xx_config_via_ac97, {0,0,0}},
ffa621a0	250	{},
d9b94f28	251	};
d9b94f28	252
f2cff6b1 ES	253	static struct pci_controller pci1_hose = {
f2cff6b1 ES	254	config_table: pci_mpc85xxcds_config_table};
d9b94f28 JL	255	#endif /* CONFIG_PCI */
d9b94f28 JL	256
f2cff6b1 ES	257	#ifdef CONFIG_PCI2
	258	static struct pci_controller pci2_hose;
	259	#endif /* CONFIG_PCI2 */
	260
	261	#ifdef CONFIG_PCIE1
	262	static struct pci_controller pcie1_hose;
	263	#endif /* CONFIG_PCIE1 */
	264
7b626880	265	void pci_init_board(void)
d9b94f28	266	{
6d0f6bcf	267	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
7b626880 KG	268	struct fsl_pci_info pci_info[4];
	269	u32 devdisr, pordevsr, io_sel;
	270	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	271	int first_free_busno = 0;
	272	int num = 0;
f2cff6b1	273
7b626880	274	int pcie_ep, pcie_configured;
f2cff6b1	275
7b626880 KG	276	devdisr = in_be32(&gur->devdisr);
	277	pordevsr = in_be32(&gur->pordevsr);
	278	porpllsr = in_be32(&gur->porpllsr);
	279	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
f2cff6b1	280
7b626880	281	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
f2cff6b1	282
7b626880 KG	283	#ifdef CONFIG_PCI1
	284	pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
	285	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
	286	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	287	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	288
	289	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	290	SET_STD_PCI_INFO(pci_info[num], 1);
	291	pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
	292	printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
f2cff6b1 ES	293	(pci_32) ? 32 : 64,
	294	(pci_speed == 33333000) ? "33" :
	295	(pci_speed == 66666000) ? "66" : "unknown",
	296	pci_clk_sel ? "sync" : "async",
	297	pci_agent ? "agent" : "host",
7b626880 KG	298	pci_arb ? "arbiter" : "external-arbiter",
	299	pci_info[num].regs);
	300
	301	first_free_busno = fsl_pci_init_port(&pci_info[num++],
	302	&pci1_hose, first_free_busno);
	303
f2cff6b1	304	#ifdef CONFIG_PCIX_CHECK
7b626880	305	if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
f2cff6b1 ES	306	/* PCI-X init */
	307	if (CONFIG_SYS_CLK_FREQ < 66000000)
	308	printf("PCI-X will only work at 66 MHz\n");
	309
	310	reg16 = PCI_X_CMD_MAX_SPLIT \| PCI_X_CMD_MAX_READ
	311	\| PCI_X_CMD_ERO \| PCI_X_CMD_DPERR_E;
	312	pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
	313	}
d9b94f28	314	#endif
f2cff6b1 ES	315	} else {
	316	printf (" PCI: disabled\n");
	317	}
7b626880 KG	318
7b626880 KG	319	puts("\n");
f2cff6b1	320	#else
7b626880	321	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
f2cff6b1 ES	322	#endif
	323
	324	#ifdef CONFIG_PCI2
	325	{
7b626880	326	uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
f2cff6b1 ES	327	uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
	328	if (pci_dual) {
	329	printf (" PCI2: 32 bit, 66 MHz, %s\n",
	330	pci2_clk_sel ? "sync" : "async");
	331	} else {
	332	printf (" PCI2: disabled\n");
	333	}
	334	}
	335	#else
7b626880	336	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
f2cff6b1 ES	337	#endif /* CONFIG_PCI2 */
	338
	339	#ifdef CONFIG_PCIE1
7b626880	340	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
f2cff6b1	341
7b626880 KG	342	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	343	SET_STD_PCIE_INFO(pci_info[num], 1);
	344	pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
	345	printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
64917ca3	346	pcie_ep ? "Endpoint" : "Root Complex",
7b626880	347	pci_info[num].regs);
f2cff6b1	348
7b626880 KG	349	first_free_busno = fsl_pci_init_port(&pci_info[num++],
7b626880 KG	350	&pcie1_hose, first_free_busno);
f2cff6b1	351	} else {
7b626880	352	printf (" PCIE1: disabled\n");
f2cff6b1	353	}
7b626880 KG	354
7b626880 KG	355	puts("\n");
f2cff6b1	356	#else
7b626880	357	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
f2cff6b1	358	#endif
d9b94f28	359	}
09f3e09e AF	360
	361	int last_stage_init(void)
	362	{
f5012827	363	unsigned short temp;
09f3e09e AF	364
	365	/* Change the resistors for the PHY */
	366	/* This is needed to get the RGMII working for the 1.3+
	367	* CDS cards */
	368	if (get_board_version() == 0x13) {
255a3577	369	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	370	TSEC1_PHY_ADDR, 29, 18);
09f3e09e AF	371
255a3577	372	miiphy_read(CONFIG_TSEC1_NAME,
09f3e09e AF	373	TSEC1_PHY_ADDR, 30, &temp);
	374
	375	temp = (temp & 0xf03f);
	376	temp \|= 2 << 9; /* 36 ohm */
	377	temp \|= 2 << 6; /* 39 ohm */
	378
255a3577	379	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	380	TSEC1_PHY_ADDR, 30, temp);
09f3e09e AF	381
255a3577	382	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	383	TSEC1_PHY_ADDR, 29, 3);
09f3e09e AF	384
255a3577	385	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	386	TSEC1_PHY_ADDR, 30, 0x8000);
	387	}
	388
	389	return 0;
	390	}
f2cff6b1 ES	391
f2cff6b1 ES	392
b90d2549	393	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea KG	394	void ft_pci_setup(void blob, bd_t bd)
2dba0dea KG	395	{
f2cff6b1	396	#ifdef CONFIG_PCI1
2dba0dea	397	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
f2cff6b1	398	#endif
f2cff6b1	399	#ifdef CONFIG_PCIE1
2dba0dea	400	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
f2cff6b1 ES	401	#endif
	402	}
	403	#endif