[people/ms/u-boot.git] / board / freescale / mpc8548cds / mpc8548cds.c

/*
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

#include "../common/cadmus.h"
#include "../common/eeprom.h"
#include "../common/via.h"

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

DECLARE_GLOBAL_DATA_PTR;

void local_bus_init(void);
void sdram_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);

	/* PCI slot in USER bits CSR[6:7] by convention. */
	uint pci_slot = get_pci_slot ();

	uint cpu_board_rev = get_cpu_board_revision ();
	uint svr;

	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
		get_board_version (), pci_slot);

	printf ("CPU Board Revision %d.%d (0x%04x)\n",
		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	svr = get_svr();

	/*
	 * Fix CPU2 errata: A core hang possible while executing a
	 * msync instruction and a snoopable transaction from an I/O
	 * master tagged to make quick forward progress is present.
	 * Fixed in Silicon Rev.2.1
	 */
	if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
		ecm->eebpcr |= (1 << 16);

	/*
	 * Hack TSEC 3 and 4 IO voltages.
	 */
	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */

	ecm->eedr = 0xffffffff;		/* clear ecm errors */
	ecm->eeer = 0xffffffff;		/* enable ecm errors */
	return 0;
}

long int
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif
	dram_size = spd_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & 0x0f) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)

	uint idx;
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
	uint cpu_board_rev;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CFG_OR2_PRELIM;
	asm("msync");

	lbc->br2 = CFG_BR2_PRELIM;
	asm("msync");

	lbc->lbcr = CFG_LBC_LBCR;
	asm("msync");


	lbc->lsrt = CFG_LBC_LSRT;
	lbc->mrtpr = CFG_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8548 uses "new" 15-16 style addressing.
	 */
	cpu_board_rev = get_cpu_board_revision();
	lsdmr_common = CFG_LBC_LSDMR_COMMON;
	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CFG_MEMTEST_START,
	       CFG_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
 * different device.  Work around that by refusing to configure it.
 */
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }

static struct pci_config_table pci_mpc85xxcds_config_table[] = {
	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
		mpc85xx_config_via_usbide, {0,0,0}},
	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
		mpc85xx_config_via_usb, {0,0,0}},
	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
		mpc85xx_config_via_usb2, {0,0,0}},
	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
		mpc85xx_config_via_power, {0,0,0}},
	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
		mpc85xx_config_via_ac97, {0,0,0}},
	{},
};

static struct pci_controller pci1_hose = {
	config_table: pci_mpc85xxcds_config_table};
#endif	/* CONFIG_PCI */

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif	/* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif	/* CONFIG_PCIE1 */

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;


#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;
	struct pci_config_table *table;

	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */

	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);

	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */

	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter"
			);


		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);


		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCI1_MEM_BASE,
			       CFG_PCI1_MEM_PHYS,
			       CFG_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCI1_IO_BASE,
			       CFG_PCI1_IO_PHYS,
			       CFG_PCI1_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = 3;

		/* relocate config table pointers */
		hose->config_table = \
			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
		for (table = hose->config_table; table && table->vendor; table++)
			table->config_device += gd->reloc_off;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
#ifdef CONFIG_PCIX_CHECK
		if (!(gur->pordevsr & PORDEVSR_PCI)) {
			/* PCI-X init */
			if (CONFIG_SYS_CLK_FREQ < 66000000)
				printf("PCI-X will only work at 66 MHz\n");

			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
		}
#endif
	} else {
		printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif

#ifdef CONFIG_PCI2
{
	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
	if (pci_dual) {
		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
			pci2_clk_sel ? "sync" : "async");
	} else {
		printf ("    PCI2: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
#endif /* CONFIG_PCI2 */

#ifdef CONFIG_PCIE1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);

	int pcie_configured  = io_sel >= 1;

	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE connected to slot as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);

		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCIE1_MEM_BASE,
			       CFG_PCIE1_MEM_PHYS,
			       CFG_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCIE1_IO_BASE,
			       CFG_PCIE1_IO_PHYS,
			       CFG_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);

		first_free_busno=hose->last_busno+1;

	} else {
		printf ("    PCIE: disabled\n");
	}
 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

}

int last_stage_init(void)
{
	unsigned short temp;

	/* Change the resistors for the PHY */
	/* This is needed to get the RGMII working for the 1.3+
	 * CDS cards */
	if (get_board_version() ==  0x13) {
		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 18);

		miiphy_read(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, &temp);

		temp = (temp & 0xf03f);
		temp |= 2 << 9;		/* 36 ohm */
		temp |= 2 << 6;		/* 39 ohm */

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, temp);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 29, 3);

		miiphy_write(CONFIG_TSEC1_NAME,
				TSEC1_PHY_ADDR, 30, 0x8000);
	}

	return 0;
}


#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_pci_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI1
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
#ifdef CONFIG_PCIE1
		path = fdt_getprop(blob, node, "pci1", NULL);
		if (path) {
			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
d9b94f28	1	/*
f2cff6b1	2	* Copyright 2004, 2007 Freescale Semiconductor.
d9b94f28 JL	3	*
	4	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
	28	#include <asm/immap_85xx.h>
f2cff6b1	29	#include <asm/immap_fsl_pci.h>
a30a549a	30	#include <spd_sdram.h>
09f3e09e	31	#include <miiphy.h>
b90d2549 KG	32	#include <libfdt.h>
b90d2549 KG	33	#include <fdt_support.h>
d9b94f28 JL	34
	35	#include "../common/cadmus.h"
	36	#include "../common/eeprom.h"
bf1dfffd	37	#include "../common/via.h"
d9b94f28 JL	38
	39	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	40	extern void ddr_enable_ecc(unsigned int dram_size);
	41	#endif
	42
f2cff6b1 ES	43	DECLARE_GLOBAL_DATA_PTR;
f2cff6b1 ES	44
d9b94f28 JL	45	void local_bus_init(void);
	46	void sdram_init(void);
	47
	48	int board_early_init_f (void)
	49	{
	50	return 0;
	51	}
	52
	53	int checkboard (void)
	54	{
f59b55a5	55	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
04db4008	56	volatile ccsr_local_ecm_t ecm = (void )(CFG_MPC85xx_ECM_ADDR);
d9b94f28 JL	57
	58	/* PCI slot in USER bits CSR[6:7] by convention. */
	59	uint pci_slot = get_pci_slot ();
	60
d9b94f28	61	uint cpu_board_rev = get_cpu_board_revision ();
66f5fa92	62	uint svr;
d9b94f28 JL	63
	64	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
	65	get_board_version (), pci_slot);
	66
	67	printf ("CPU Board Revision %d.%d (0x%04x)\n",
	68	MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
	69	MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
d9b94f28 JL	70	/*
	71	* Initialize local bus.
	72	*/
	73	local_bus_init ();
	74
66f5fa92 AF	75	svr = get_svr();
66f5fa92 AF	76
7337b237 ZR	77	/*
	78	* Fix CPU2 errata: A core hang possible while executing a
	79	* msync instruction and a snoopable transaction from an I/O
	80	* master tagged to make quick forward progress is present.
66f5fa92	81	* Fixed in Silicon Rev.2.1
7337b237	82	*/
66f5fa92 AF	83	if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
66f5fa92 AF	84	ecm->eebpcr \|= (1 << 16);
d9b94f28 JL	85
	86	/*
	87	* Hack TSEC 3 and 4 IO voltages.
	88	*/
	89	gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
	90
f2cff6b1 ES	91	ecm->eedr = 0xffffffff; /* clear ecm errors */
f2cff6b1 ES	92	ecm->eeer = 0xffffffff; /* enable ecm errors */
d9b94f28 JL	93	return 0;
	94	}
	95
	96	long int
	97	initdram(int board_type)
	98	{
	99	long dram_size = 0;
d9b94f28 JL	100
	101	puts("Initializing\n");
	102
	103	#if defined(CONFIG_DDR_DLL)
	104	{
	105	/*
	106	* Work around to stabilize DDR DLL MSYNC_IN.
	107	* Errata DDR9 seems to have been fixed.
	108	* This is now the workaround for Errata DDR11:
	109	* Override DLL = 1, Course Adj = 1, Tap Select = 0
	110	*/
	111
f59b55a5	112	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
d9b94f28 JL	113
	114	gur->ddrdllcr = 0x81000000;
	115	asm("sync;isync;msync");
	116	udelay(200);
	117	}
	118	#endif
	119	dram_size = spd_sdram();
	120
	121	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	122	/*
	123	* Initialize and enable DDR ECC.
	124	*/
	125	ddr_enable_ecc(dram_size);
	126	#endif
	127	/*
	128	* SDRAM Initialization
	129	*/
	130	sdram_init();
	131
	132	puts(" DDR: ");
	133	return dram_size;
	134	}
	135
	136	/*
	137	* Initialize Local Bus
	138	*/
	139	void
	140	local_bus_init(void)
	141	{
f59b55a5	142	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
04db4008	143	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
d9b94f28 JL	144
	145	uint clkdiv;
	146	uint lbc_hz;
	147	sys_info_t sysinfo;
	148
	149	get_sys_info(&sysinfo);
	150	clkdiv = (lbc->lcrr & 0x0f) * 2;
	151	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	152
	153	gur->lbiuiplldcr1 = 0x00078080;
	154	if (clkdiv == 16) {
	155	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	156	} else if (clkdiv == 8) {
	157	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	158	} else if (clkdiv == 4) {
	159	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	160	}
	161
	162	lbc->lcrr \|= 0x00030000;
	163
	164	asm("sync;isync;msync");
f2cff6b1 ES	165
	166	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	167	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
d9b94f28 JL	168	}
	169
	170	/*
	171	* Initialize SDRAM memory on the Local Bus.
	172	*/
	173	void
	174	sdram_init(void)
	175	{
	176	#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	177
	178	uint idx;
04db4008	179	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
d9b94f28 JL	180	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
	181	uint cpu_board_rev;
	182	uint lsdmr_common;
	183
	184	puts(" SDRAM: ");
	185
	186	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
	187
	188	/*
	189	* Setup SDRAM Base and Option Registers
	190	*/
	191	lbc->or2 = CFG_OR2_PRELIM;
	192	asm("msync");
	193
	194	lbc->br2 = CFG_BR2_PRELIM;
	195	asm("msync");
	196
	197	lbc->lbcr = CFG_LBC_LBCR;
	198	asm("msync");
	199
	200
	201	lbc->lsrt = CFG_LBC_LSRT;
	202	lbc->mrtpr = CFG_LBC_MRTPR;
	203	asm("msync");
	204
	205	/*
	206	* MPC8548 uses "new" 15-16 style addressing.
	207	*/
	208	cpu_board_rev = get_cpu_board_revision();
	209	lsdmr_common = CFG_LBC_LSDMR_COMMON;
	210	lsdmr_common \|= CFG_LBC_LSDMR_BSMA1516;
	211
	212	/*
	213	* Issue PRECHARGE ALL command.
	214	*/
	215	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_PCHALL;
	216	asm("sync;msync");
	217	*sdram_addr = 0xff;
	218	ppcDcbf((unsigned long) sdram_addr);
	219	udelay(100);
	220
	221	/*
	222	* Issue 8 AUTO REFRESH commands.
	223	*/
	224	for (idx = 0; idx < 8; idx++) {
	225	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_ARFRSH;
	226	asm("sync;msync");
	227	*sdram_addr = 0xff;
	228	ppcDcbf((unsigned long) sdram_addr);
	229	udelay(100);
	230	}
	231
	232	/*
	233	* Issue 8 MODE-set command.
	234	*/
	235	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_MRW;
	236	asm("sync;msync");
	237	*sdram_addr = 0xff;
	238	ppcDcbf((unsigned long) sdram_addr);
	239	udelay(100);
	240
	241	/*
	242	* Issue NORMAL OP command.
	243	*/
244	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_NORMAL;
245	asm("sync;msync");
246	*sdram_addr = 0xff;
247	ppcDcbf((unsigned long) sdram_addr);
248	udelay(200); /* Overkill. Must wait > 200 bus cycles */
249
250	#endif /* enable SDRAM init */
251	}
252
253	#if defined(CFG_DRAM_TEST)
254	int
255	testdram(void)
256	{
257	uint pstart = (uint ) CFG_MEMTEST_START;
258	uint pend = (uint ) CFG_MEMTEST_END;
259	uint *p;
260
261	printf("Testing DRAM from 0x%08x to 0x%08x\n",
262	CFG_MEMTEST_START,
263	CFG_MEMTEST_END);
264
265	printf("DRAM test phase 1:\n");
266	for (p = pstart; p < pend; p++)
267	*p = 0xaaaaaaaa;
268
269	for (p = pstart; p < pend; p++) {
270	if (*p != 0xaaaaaaaa) {
271	printf ("DRAM test fails at: %08x\n", (uint) p);
272	return 1;
273	}
274	}
275
276	printf("DRAM test phase 2:\n");
277	for (p = pstart; p < pend; p++)
278	*p = 0x55555555;
279
280	for (p = pstart; p < pend; p++) {
281	if (*p != 0x55555555) {
282	printf ("DRAM test fails at: %08x\n", (uint) p);
283	return 1;
284	}
285	}
286
287	printf("DRAM test passed.\n");
288	return 0;
289	}
290	#endif
291
f2cff6b1	292	#if defined(CONFIG_PCI) \|\| defined(CONFIG_PCI1)
bf1dfffd MM	293	/* For some reason the Tundra PCI bridge shows up on itself as a
bf1dfffd MM	294	* different device. Work around that by refusing to configure it.
d9b94f28	295	*/
bf1dfffd	296	void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
d9b94f28	297
d9b94f28	298	static struct pci_config_table pci_mpc85xxcds_config_table[] = {
bf1dfffd	299	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
7f3f2bd2 RV	300	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
7f3f2bd2 RV	301	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
ffa621a0	302	mpc85xx_config_via_usbide, {0,0,0}},
7f3f2bd2 RV	303	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
	304	mpc85xx_config_via_usb, {0,0,0}},
	305	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
	306	mpc85xx_config_via_usb2, {0,0,0}},
	307	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
ffa621a0	308	mpc85xx_config_via_power, {0,0,0}},
7f3f2bd2 RV	309	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
7f3f2bd2 RV	310	mpc85xx_config_via_ac97, {0,0,0}},
ffa621a0	311	{},
d9b94f28	312	};
d9b94f28	313
f2cff6b1 ES	314	static struct pci_controller pci1_hose = {
f2cff6b1 ES	315	config_table: pci_mpc85xxcds_config_table};
d9b94f28 JL	316	#endif /* CONFIG_PCI */
d9b94f28 JL	317
f2cff6b1 ES	318	#ifdef CONFIG_PCI2
	319	static struct pci_controller pci2_hose;
	320	#endif /* CONFIG_PCI2 */
	321
	322	#ifdef CONFIG_PCIE1
	323	static struct pci_controller pcie1_hose;
	324	#endif /* CONFIG_PCIE1 */
	325
	326	int first_free_busno=0;
	327
d9b94f28 JL	328	void
	329	pci_init_board(void)
	330	{
f59b55a5	331	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
f2cff6b1 ES	332	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	333	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	334
	335
	336	#ifdef CONFIG_PCI1
	337	{
	338	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI1_ADDR;
	339	extern void fsl_pci_init(struct pci_controller *hose);
	340	struct pci_controller *hose = &pci1_hose;
	341	struct pci_config_table *table;
	342
	343	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
	344	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	345	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	346
	347	uint pci_agent = (host_agent == 3) \|\| (host_agent == 4 ) \|\| (host_agent == 6);
	348
	349	uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
	350
	351	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
	352	printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
	353	(pci_32) ? 32 : 64,
	354	(pci_speed == 33333000) ? "33" :
	355	(pci_speed == 66666000) ? "66" : "unknown",
	356	pci_clk_sel ? "sync" : "async",
	357	pci_agent ? "agent" : "host",
	358	pci_arb ? "arbiter" : "external-arbiter"
	359	);
	360
	361
4bf4abb8	362	/* inbound */
f2cff6b1	363	pci_set_region(hose->regions + 0,
4bf4abb8 ES	364	CFG_PCI_MEMORY_BUS,
	365	CFG_PCI_MEMORY_PHYS,
	366	CFG_PCI_MEMORY_SIZE,
	367	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	368
	369
	370	/* outbound memory */
	371	pci_set_region(hose->regions + 1,
f2cff6b1 ES	372	CFG_PCI1_MEM_BASE,
	373	CFG_PCI1_MEM_PHYS,
	374	CFG_PCI1_MEM_SIZE,
	375	PCI_REGION_MEM);
	376
	377	/* outbound io */
4bf4abb8	378	pci_set_region(hose->regions + 2,
f2cff6b1 ES	379	CFG_PCI1_IO_BASE,
	380	CFG_PCI1_IO_PHYS,
	381	CFG_PCI1_IO_SIZE,
	382	PCI_REGION_IO);
4bf4abb8	383	hose->region_count = 3;
f2cff6b1 ES	384
	385	/* relocate config table pointers */
	386	hose->config_table = \
	387	(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
	388	for (table = hose->config_table; table && table->vendor; table++)
	389	table->config_device += gd->reloc_off;
	390
	391	hose->first_busno=first_free_busno;
	392	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	393
	394	fsl_pci_init(hose);
	395	first_free_busno=hose->last_busno+1;
	396	printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	397	#ifdef CONFIG_PCIX_CHECK
	398	if (!(gur->pordevsr & PORDEVSR_PCI)) {
	399	/* PCI-X init */
	400	if (CONFIG_SYS_CLK_FREQ < 66000000)
	401	printf("PCI-X will only work at 66 MHz\n");
	402
	403	reg16 = PCI_X_CMD_MAX_SPLIT \| PCI_X_CMD_MAX_READ
	404	\| PCI_X_CMD_ERO \| PCI_X_CMD_DPERR_E;
	405	pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
	406	}
d9b94f28	407	#endif
f2cff6b1 ES	408	} else {
	409	printf (" PCI: disabled\n");
	410	}
	411	}
	412	#else
	413	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	414	#endif
	415
	416	#ifdef CONFIG_PCI2
	417	{
	418	uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
	419	uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
	420	if (pci_dual) {
	421	printf (" PCI2: 32 bit, 66 MHz, %s\n",
	422	pci2_clk_sel ? "sync" : "async");
	423	} else {
	424	printf (" PCI2: disabled\n");
	425	}
	426	}
	427	#else
	428	gur->devdisr \|= MPC85xx_DEVDISR_PCI2; /* disable */
	429	#endif /* CONFIG_PCI2 */
	430
	431	#ifdef CONFIG_PCIE1
	432	{
	433	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCIE1_ADDR;
	434	extern void fsl_pci_init(struct pci_controller *hose);
	435	struct pci_controller *hose = &pcie1_hose;
	436	int pcie_ep = (host_agent == 0) \|\| (host_agent == 2 ) \|\| (host_agent == 3);
	437
	438	int pcie_configured = io_sel >= 1;
	439
	440	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
	441	printf ("\n PCIE connected to slot as %s (base address %x)",
	442	pcie_ep ? "End Point" : "Root Complex",
	443	(uint)pci);
	444
	445	if (pci->pme_msg_det) {
	446	pci->pme_msg_det = 0xffffffff;
	447	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	448	}
	449	printf ("\n");
	450
	451	/* inbound */
	452	pci_set_region(hose->regions + 0,
	453	CFG_PCI_MEMORY_BUS,
	454	CFG_PCI_MEMORY_PHYS,
	455	CFG_PCI_MEMORY_SIZE,
	456	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	457
	458	/* outbound memory */
	459	pci_set_region(hose->regions + 1,
	460	CFG_PCIE1_MEM_BASE,
	461	CFG_PCIE1_MEM_PHYS,
	462	CFG_PCIE1_MEM_SIZE,
	463	PCI_REGION_MEM);
	464
	465	/* outbound io */
	466	pci_set_region(hose->regions + 2,
	467	CFG_PCIE1_IO_BASE,
	468	CFG_PCIE1_IO_PHYS,
	469	CFG_PCIE1_IO_SIZE,
	470	PCI_REGION_IO);
	471
472	hose->region_count = 3;
473
474	hose->first_busno=first_free_busno;
475	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
476
477	fsl_pci_init(hose);
478	printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
479
480	first_free_busno=hose->last_busno+1;
481
482	} else {
483	printf (" PCIE: disabled\n");
484	}
485	}
486	#else
487	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
488	#endif
489
d9b94f28	490	}
09f3e09e AF	491
	492	int last_stage_init(void)
	493	{
f5012827	494	unsigned short temp;
09f3e09e AF	495
	496	/* Change the resistors for the PHY */
	497	/* This is needed to get the RGMII working for the 1.3+
	498	* CDS cards */
	499	if (get_board_version() == 0x13) {
255a3577	500	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	501	TSEC1_PHY_ADDR, 29, 18);
09f3e09e AF	502
255a3577	503	miiphy_read(CONFIG_TSEC1_NAME,
09f3e09e AF	504	TSEC1_PHY_ADDR, 30, &temp);
	505
	506	temp = (temp & 0xf03f);
	507	temp \|= 2 << 9; /* 36 ohm */
	508	temp \|= 2 << 6; /* 39 ohm */
	509
255a3577	510	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	511	TSEC1_PHY_ADDR, 30, temp);
09f3e09e AF	512
255a3577	513	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	514	TSEC1_PHY_ADDR, 29, 3);
09f3e09e AF	515
255a3577	516	miiphy_write(CONFIG_TSEC1_NAME,
09f3e09e AF	517	TSEC1_PHY_ADDR, 30, 0x8000);
	518	}
	519
	520	return 0;
	521	}
f2cff6b1 ES	522
f2cff6b1 ES	523
b90d2549	524	#if defined(CONFIG_OF_BOARD_SETUP)
f2cff6b1 ES	525	void
	526	ft_pci_setup(void blob, bd_t bd)
	527	{
b90d2549 KG	528	int node, tmp[2];
b90d2549 KG	529	const char *path;
f2cff6b1	530
b90d2549 KG	531	node = fdt_path_offset(blob, "/aliases");
	532	tmp[0] = 0;
	533	if (node >= 0) {
f2cff6b1	534	#ifdef CONFIG_PCI1
b90d2549 KG	535	path = fdt_getprop(blob, node, "pci0", NULL);
	536	if (path) {
	537	tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
	538	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	539	}
f2cff6b1	540	#endif
f2cff6b1	541	#ifdef CONFIG_PCIE1
b90d2549 KG	542	path = fdt_getprop(blob, node, "pci1", NULL);
	543	if (path) {
	544	tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
	545	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	546	}
f2cff6b1	547	#endif
b90d2549	548	}
f2cff6b1 ES	549	}
f2cff6b1 ES	550	#endif