projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 0db37dc2 | 2 | /* |
| 8b47d7ec | 3 | * Copyright 2008, 2011 Freescale Semiconductor, Inc. |
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4 | * |
| 5 | * (C) Copyright 2000 | |
| 6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
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7 | */ |
| 8 | ||
| d678a59d | 9 | #include <common.h> |
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10 | #include <asm/mmu.h> |
| 11 | ||
| 12 | struct fsl_e_tlb_entry tlb_table[] = { | |
| 13 | /* TLB 0 - for temp stack in cache */ | |
| 65cc0e2a | 14 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, |
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15 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 16 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 65cc0e2a | 17 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, |
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18 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 19 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 65cc0e2a | 20 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, |
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21 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 22 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 65cc0e2a | 23 | SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, |
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24 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 25 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
| 26 | ||
| fff80975 | 27 | /* TLB 1 */ |
| 0db37dc2 | 28 | /* |
| fff80975 | 29 | * Entry 0: |
| 30 | * FLASH(cover boot page) 16M Non-cacheable, guarded | |
| 0db37dc2 | 31 | */ |
| 65cc0e2a | 32 | SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, |
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33 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 34 | 0, 0, BOOKE_PAGESZ_16M, 1), | |
| 35 | ||
| 36 | /* | |
| fff80975 | 37 | * Entry 1: |
| 38 | * CCSRBAR 1M Non-cacheable, guarded | |
| 0db37dc2 | 39 | */ |
| 65cc0e2a | 40 | SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, |
| 0db37dc2 | 41 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| fff80975 | 42 | 0, 1, BOOKE_PAGESZ_1M, 1), |
| 0db37dc2 | 43 | |
| 0db37dc2 | 44 | /* |
| fff80975 | 45 | * Entry 2: |
| 46 | * LBC SDRAM 64M Cacheable, non-guarded | |
| 0db37dc2 | 47 | */ |
| 65cc0e2a TR |
48 | SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE, |
| 49 | CFG_SYS_LBC_SDRAM_BASE_PHYS, | |
| 316f0d0f | 50 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, |
| fff80975 | 51 | 0, 2, BOOKE_PAGESZ_64M, 1), |
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52 | |
| 53 | /* | |
| fff80975 | 54 | * Entry 3: |
| 55 | * CADMUS registers 1M Non-cacheable, guarded | |
| 0db37dc2 | 56 | */ |
| fff80975 | 57 | SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, |
| 0db37dc2 | 58 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| fff80975 | 59 | 0, 3, BOOKE_PAGESZ_1M, 1), |
| 8b47d7ec | 60 | |
| 0db37dc2 | 61 | /* |
| fff80975 | 62 | * Entry 4: |
| 63 | * PCI and PCIe MEM 1G Non-cacheable, guarded | |
| 0db37dc2 | 64 | */ |
| ecc8d425 | 65 | SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS, |
| 0db37dc2 | 66 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| fff80975 | 67 | 0, 4, BOOKE_PAGESZ_1G, 1), |
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68 | |
| 69 | /* | |
| fff80975 | 70 | * Entry 5: |
| 71 | * PCI1 IO 1M Non-cacheable, guarded | |
| 0db37dc2 | 72 | */ |
| ecc8d425 | 73 | SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS, |
| fff80975 | 74 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 75 | 0, 5, BOOKE_PAGESZ_1M, 1), | |
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76 | |
| 77 | /* | |
| fff80975 | 78 | * Entry 6: |
| 79 | * PCIe IO 1M Non-cacheable, guarded | |
| 0db37dc2 | 80 | */ |
| ecc8d425 | 81 | SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, |
| fff80975 | 82 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 83 | 0, 6, BOOKE_PAGESZ_1M, 1), | |
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84 | }; |
| 85 | ||
| 86 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |