[thirdparty/u-boot.git] / board / freescale / p1_p2_rdb_pc / ddr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <vsprintf.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if	defined(CONFIG_P1020RDB_PROTO)
/* Micron MT41J256M8_187E */
dimm_params_t ddr_raw_timing = {
	.n_ranks = 1,
	.rank_density = 1073741824u,
	.capacity = 1073741824u,
	.primary_sdram_width = 32,
	.ec_sdram_width = 0,
	.registered_dimm = 0,
	.mirrored_dimm = 0,
	.n_row_addr = 15,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 0,
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1870,
	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
	.taa_ps = 13125,
	.twr_ps = 15000,
	.trcd_ps = 13125,
	.trrd_ps = 7500,
	.trp_ps = 13125,
	.tras_ps = 37500,
	.trc_ps = 50625,
	.trfc_ps = 160000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 37500,
};
#elif defined(CONFIG_TARGET_P2020RDB)
/* Micron MT41J128M16_15E */
dimm_params_t ddr_raw_timing = {
	.n_ranks = 1,
	.rank_density = 1073741824u,
	.capacity = 1073741824u,
	.primary_sdram_width = 64,
	.ec_sdram_width = 0,
	.registered_dimm = 0,
	.mirrored_dimm = 0,
	.n_row_addr = 14,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 0,
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1500,
	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
	.taa_ps = 13500,
	.twr_ps = 15000,
	.trcd_ps = 13500,
	.trrd_ps = 6000,
	.trp_ps = 13500,
	.tras_ps = 36000,
	.trc_ps = 49500,
	.trfc_ps = 160000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 30000,
};
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
	.n_ranks = 2,
	.rank_density = 1073741824u,
	.capacity = 2147483648u,
	.primary_sdram_width = 32,
	.ec_sdram_width = 0,
	.registered_dimm = 0,
	.mirrored_dimm = 0,
	.n_row_addr = 15,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 0,
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1870,
	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
	.taa_ps = 13125,
	.twr_ps = 15000,
	.trcd_ps = 13125,
	.trrd_ps = 7500,
	.trp_ps = 13125,
	.tras_ps = 37500,
	.trc_ps = 50625,
	.trfc_ps = 160000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 37500,
};
#elif defined(CONFIG_TARGET_P1020RDB_PC)
/*
 * Samsung K4B2G0846C-HCF8
 * The following timing are for "downshift"
 * i.e. to use CL9 part as CL7
 * otherwise, tAA, tRCD, tRP will be 13500ps
 * and tRC will be 49500ps
 */
dimm_params_t ddr_raw_timing = {
	.n_ranks = 1,
	.rank_density = 1073741824u,
	.capacity = 1073741824u,
	.primary_sdram_width = 32,
	.ec_sdram_width = 0,
	.registered_dimm = 0,
	.mirrored_dimm = 0,
	.n_row_addr = 15,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 0,
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1875,
	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
	.taa_ps = 13125,
	.twr_ps = 15000,
	.trcd_ps = 13125,
	.trrd_ps = 7500,
	.trp_ps = 13125,
	.tras_ps = 37500,
	.trc_ps = 50625,
	.trfc_ps = 160000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 37500,
};
#elif	defined(CONFIG_TARGET_P1024RDB)
/*
 * Samsung K4B2G0846C-HCH9
 * The following timing are for "downshift"
 * i.e. to use CL9 part as CL7
 * otherwise, tAA, tRCD, tRP will be 13500ps
 * and tRC will be 49500ps
 */
dimm_params_t ddr_raw_timing = {
	.n_ranks = 1,
	.rank_density = 1073741824u,
	.capacity = 1073741824u,
	.primary_sdram_width = 32,
	.ec_sdram_width = 0,
	.registered_dimm = 0,
	.mirrored_dimm = 0,
	.n_row_addr = 15,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 0,
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1500,
	.caslat_x = 0x3e << 4,	/* 5,6,7,8,9 */
	.taa_ps = 13125,
	.twr_ps = 15000,
	.trcd_ps = 13125,
	.trrd_ps = 6000,
	.trp_ps = 13125,
	.tras_ps = 36000,
	.trc_ps = 49125,
	.trfc_ps = 160000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 30000,
};
#else
#error Missing raw timing data for this board
#endif

int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
		unsigned int controller_number,
		unsigned int dimm_number)
{
	const char dimm_model[] = "Fixed DDR on board";

	if ((controller_number == 0) && (dimm_number == 0)) {
		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
	}

	return 0;
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */

#ifdef CFG_SYS_DDR_CS0_BNDS
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
	sys_info_t sysinfo;
	char buf[32];
	size_t ddr_size;
	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
		.cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
		.cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
		.cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
		.cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
		.cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
		.cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
#endif
		.timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
		.timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
		.timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
		.timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
		.ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
		.ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
		.ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
		.ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
		.ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
		.ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
		.ddr_data_init = 0xdeadbeef, /* Poison value */
		.ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
		.ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
		.ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
		.timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
		.timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
		.ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
		.ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
		.ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
		.ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
		.ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
	};

	get_sys_info(&sysinfo);
	printf("Configuring DDR for %s MT/s data rate\n",
			strmhz(buf, sysinfo.freq_ddrbus));

	ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;

	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	};

	return ddr_size;
}
#endif

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	int i;
	popts->clk_adjust = 6;
	popts->cpo_override = 0x1f;
	popts->write_data_delay = 2;
	popts->half_strength_driver_enable = 1;
	/* Write leveling override */
	popts->wrlvl_en = 1;
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;
	popts->wrlvl_start = 0x8;
	popts->trwt_override = 1;
	popts->trwt = 0;

	if (pdimm->primary_sdram_width == 64)
		popts->data_bus_width = 0;
	else if (pdimm->primary_sdram_width == 32)
		popts->data_bus_width = 1;
	else
		printf("Error in DDR bus width configuration!\n");

	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
14aa71e6 LY	2	/*
14aa71e6 LY	3	* Copyright 2010-2011 Freescale Semiconductor, Inc.
14aa71e6 LY	4	*/
14aa71e6 LY	5
d678a59d	6	#include <common.h>
2189d5f1	7	#include <vsprintf.h>
14aa71e6 LY	8	#include <asm/mmu.h>
14aa71e6 LY	9	#include <asm/immap_85xx.h>
d678a59d	10	#include <asm/processor.h>
5614e71b YS	11	#include <fsl_ddr_sdram.h>
5614e71b YS	12	#include <fsl_ddr_dimm_params.h>
14aa71e6 LY	13	#include <asm/io.h>
	14	#include <asm/fsl_law.h>
	15
1ba62f10	16	#ifdef CONFIG_SYS_DDR_RAW_TIMING
6d1dd76a	17	#if defined(CONFIG_P1020RDB_PROTO)
14aa71e6 LY	18	/* Micron MT41J256M8_187E */
	19	dimm_params_t ddr_raw_timing = {
	20	.n_ranks = 1,
	21	.rank_density = 1073741824u,
	22	.capacity = 1073741824u,
	23	.primary_sdram_width = 32,
	24	.ec_sdram_width = 0,
	25	.registered_dimm = 0,
	26	.mirrored_dimm = 0,
	27	.n_row_addr = 15,
	28	.n_col_addr = 10,
	29	.n_banks_per_sdram_device = 8,
	30	.edc_config = 0,
	31	.burst_lengths_bitmask = 0x0c,
	32
0dd38a35 PJ	33	.tckmin_x_ps = 1870,
	34	.caslat_x = 0x1e << 4, /* 5,6,7,8 */
	35	.taa_ps = 13125,
	36	.twr_ps = 15000,
	37	.trcd_ps = 13125,
	38	.trrd_ps = 7500,
	39	.trp_ps = 13125,
	40	.tras_ps = 37500,
	41	.trc_ps = 50625,
	42	.trfc_ps = 160000,
	43	.twtr_ps = 7500,
	44	.trtp_ps = 7500,
14aa71e6	45	.refresh_rate_ps = 7800000,
0dd38a35	46	.tfaw_ps = 37500,
14aa71e6	47	};
8435aa77	48	#elif defined(CONFIG_TARGET_P2020RDB)
14aa71e6 LY	49	/* Micron MT41J128M16_15E */
	50	dimm_params_t ddr_raw_timing = {
	51	.n_ranks = 1,
	52	.rank_density = 1073741824u,
	53	.capacity = 1073741824u,
	54	.primary_sdram_width = 64,
	55	.ec_sdram_width = 0,
	56	.registered_dimm = 0,
	57	.mirrored_dimm = 0,
	58	.n_row_addr = 14,
	59	.n_col_addr = 10,
	60	.n_banks_per_sdram_device = 8,
	61	.edc_config = 0,
	62	.burst_lengths_bitmask = 0x0c,
	63
0dd38a35 PJ	64	.tckmin_x_ps = 1500,
	65	.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
	66	.taa_ps = 13500,
	67	.twr_ps = 15000,
	68	.trcd_ps = 13500,
	69	.trrd_ps = 6000,
	70	.trp_ps = 13500,
	71	.tras_ps = 36000,
	72	.trc_ps = 49500,
	73	.trfc_ps = 160000,
	74	.twtr_ps = 7500,
	75	.trtp_ps = 7500,
14aa71e6	76	.refresh_rate_ps = 7800000,
0dd38a35	77	.tfaw_ps = 30000,
14aa71e6	78	};
f404b66c	79	#elif (defined(CONFIG_TARGET_P1020MBG) \|\| defined(CONFIG_TARGET_P1020RDB_PD))
14aa71e6 LY	80	/* Micron MT41J512M8_187E */
	81	dimm_params_t ddr_raw_timing = {
	82	.n_ranks = 2,
	83	.rank_density = 1073741824u,
	84	.capacity = 2147483648u,
	85	.primary_sdram_width = 32,
	86	.ec_sdram_width = 0,
	87	.registered_dimm = 0,
	88	.mirrored_dimm = 0,
	89	.n_row_addr = 15,
	90	.n_col_addr = 10,
	91	.n_banks_per_sdram_device = 8,
	92	.edc_config = 0,
	93	.burst_lengths_bitmask = 0x0c,
	94
0dd38a35 PJ	95	.tckmin_x_ps = 1870,
	96	.caslat_x = 0x1e << 4, /* 5,6,7,8 */
	97	.taa_ps = 13125,
	98	.twr_ps = 15000,
	99	.trcd_ps = 13125,
	100	.trrd_ps = 7500,
	101	.trp_ps = 13125,
	102	.tras_ps = 37500,
	103	.trc_ps = 50625,
	104	.trfc_ps = 160000,
	105	.twtr_ps = 7500,
	106	.trtp_ps = 7500,
14aa71e6	107	.refresh_rate_ps = 7800000,
0dd38a35	108	.tfaw_ps = 37500,
14aa71e6	109	};
aa14620c	110	#elif defined(CONFIG_TARGET_P1020RDB_PC)
14aa71e6 LY	111	/*
	112	* Samsung K4B2G0846C-HCF8
	113	* The following timing are for "downshift"
	114	* i.e. to use CL9 part as CL7
	115	* otherwise, tAA, tRCD, tRP will be 13500ps
	116	* and tRC will be 49500ps
	117	*/
	118	dimm_params_t ddr_raw_timing = {
	119	.n_ranks = 1,
	120	.rank_density = 1073741824u,
	121	.capacity = 1073741824u,
	122	.primary_sdram_width = 32,
	123	.ec_sdram_width = 0,
	124	.registered_dimm = 0,
	125	.mirrored_dimm = 0,
	126	.n_row_addr = 15,
	127	.n_col_addr = 10,
	128	.n_banks_per_sdram_device = 8,
	129	.edc_config = 0,
	130	.burst_lengths_bitmask = 0x0c,
	131
0dd38a35 PJ	132	.tckmin_x_ps = 1875,
	133	.caslat_x = 0x1e << 4, /* 5,6,7,8 */
	134	.taa_ps = 13125,
	135	.twr_ps = 15000,
	136	.trcd_ps = 13125,
	137	.trrd_ps = 7500,
	138	.trp_ps = 13125,
	139	.tras_ps = 37500,
	140	.trc_ps = 50625,
	141	.trfc_ps = 160000,
	142	.twtr_ps = 7500,
	143	.trtp_ps = 7500,
14aa71e6	144	.refresh_rate_ps = 7800000,
0dd38a35	145	.tfaw_ps = 37500,
14aa71e6	146	};
d521cece	147	#elif defined(CONFIG_TARGET_P1024RDB)
14aa71e6 LY	148	/*
	149	* Samsung K4B2G0846C-HCH9
	150	* The following timing are for "downshift"
	151	* i.e. to use CL9 part as CL7
	152	* otherwise, tAA, tRCD, tRP will be 13500ps
	153	* and tRC will be 49500ps
	154	*/
	155	dimm_params_t ddr_raw_timing = {
	156	.n_ranks = 1,
	157	.rank_density = 1073741824u,
	158	.capacity = 1073741824u,
	159	.primary_sdram_width = 32,
	160	.ec_sdram_width = 0,
	161	.registered_dimm = 0,
	162	.mirrored_dimm = 0,
	163	.n_row_addr = 15,
	164	.n_col_addr = 10,
	165	.n_banks_per_sdram_device = 8,
	166	.edc_config = 0,
	167	.burst_lengths_bitmask = 0x0c,
	168
0dd38a35 PJ	169	.tckmin_x_ps = 1500,
	170	.caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
	171	.taa_ps = 13125,
	172	.twr_ps = 15000,
	173	.trcd_ps = 13125,
	174	.trrd_ps = 6000,
	175	.trp_ps = 13125,
	176	.tras_ps = 36000,
	177	.trc_ps = 49125,
	178	.trfc_ps = 160000,
	179	.twtr_ps = 7500,
	180	.trtp_ps = 7500,
14aa71e6	181	.refresh_rate_ps = 7800000,
0dd38a35	182	.tfaw_ps = 30000,
14aa71e6 LY	183	};
	184	#else
	185	#error Missing raw timing data for this board
	186	#endif
	187
	188	int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
	189	unsigned int controller_number,
	190	unsigned int dimm_number)
	191	{
	192	const char dimm_model[] = "Fixed DDR on board";
	193
	194	if ((controller_number == 0) && (dimm_number == 0)) {
	195	memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
	196	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	197	memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
	198	}
	199
	200	return 0;
	201	}
1ba62f10	202	#endif /* CONFIG_SYS_DDR_RAW_TIMING */
14aa71e6	203
65cc0e2a	204	#ifdef CFG_SYS_DDR_CS0_BNDS
14aa71e6 LY	205	/* Fixed sdram init -- doesn't use serial presence detect. */
	206	phys_size_t fixed_sdram(void)
	207	{
	208	sys_info_t sysinfo;
	209	char buf[32];
	210	size_t ddr_size;
	211	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
65cc0e2a TR	212	.cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
	213	.cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
	214	.cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
14aa71e6	215	#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
65cc0e2a TR	216	.cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
	217	.cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
	218	.cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
14aa71e6	219	#endif
65cc0e2a TR	220	.timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
	221	.timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
	222	.timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
	223	.timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
	224	.ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
	225	.ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
	226	.ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
	227	.ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
	228	.ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
	229	.ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
07ef80cd	230	.ddr_data_init = 0xdeadbeef, /* Poison value */
65cc0e2a TR	231	.ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
	232	.ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
	233	.ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
	234	.timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
	235	.timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
	236	.ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
	237	.ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
	238	.ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
	239	.ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
	240	.ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
14aa71e6 LY	241	};
	242
	243	get_sys_info(&sysinfo);
	244	printf("Configuring DDR for %s MT/s data rate\n",
997399fa	245	strmhz(buf, sysinfo.freq_ddrbus));
14aa71e6	246
aa6e94de	247	ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
14aa71e6	248
c63e1370	249	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
14aa71e6	250
65cc0e2a	251	if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
14aa71e6 LY	252	ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
	253	printf("ERROR setting Local Access Windows for DDR\n");
	254	return 0;
	255	};
	256
	257	return ddr_size;
	258	}
13d1143f	259	#endif
14aa71e6 LY	260
	261	void fsl_ddr_board_options(memctl_options_t *popts,
	262	dimm_params_t *pdimm,
	263	unsigned int ctrl_num)
	264	{
	265	int i;
	266	popts->clk_adjust = 6;
	267	popts->cpo_override = 0x1f;
	268	popts->write_data_delay = 2;
	269	popts->half_strength_driver_enable = 1;
	270	/* Write leveling override */
	271	popts->wrlvl_en = 1;
	272	popts->wrlvl_override = 1;
	273	popts->wrlvl_sample = 0xf;
	274	popts->wrlvl_start = 0x8;
	275	popts->trwt_override = 1;
	276	popts->trwt = 0;
	277
	278	if (pdimm->primary_sdram_width == 64)
	279	popts->data_bus_width = 0;
	280	else if (pdimm->primary_sdram_width == 32)
	281	popts->data_bus_width = 1;
	282	else
	283	printf("Error in DDR bus width configuration!\n");
	284
	285	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
	286	popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
	287	popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
	288	}
	289	}