[thirdparty/u-boot.git] / board / freescale / t102xrdb / eth_t102xrdb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
 */

#include <common.h>
#include <command.h>
#include <fdt_support.h>
#include <net.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/fman.h"

int board_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FMAN_ENET)
	int i, interface;
	struct memac_mdio_info dtsec_mdio_info;
	struct memac_mdio_info tgec_mdio_info;
	struct mii_dev *dev;
	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_s1;

	srds_s1 = in_be32(&gur->rcwsr[4]) &
					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;

	dtsec_mdio_info.regs =
		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;

	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

	/* Register the 1G MDIO bus */
	fm_memac_mdio_init(bis, &dtsec_mdio_info);

	tgec_mdio_info.regs =
		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;

	/* Register the 10G MDIO bus */
	fm_memac_mdio_init(bis, &tgec_mdio_info);

	/* Set the on-board RGMII PHY address */
	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);

	switch (srds_s1) {
#ifdef CONFIG_TARGET_T1024RDB
	case 0x95:
		/* set the on-board RGMII2  PHY */
		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);

		/* set 10GBase-R with Aquantia AQR105 PHY */
		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
		break;
#endif
	case 0x6a:
	case 0x6b:
	case 0x77:
	case 0x135:
		/* set the on-board 2.5G SGMII AQR105 PHY */
		fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
#ifdef CONFIG_TARGET_T1023RDB
		/* set the on-board 1G SGMII RTL8211F PHY */
		fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
#endif
		break;
	default:
		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
		       srds_s1);
		break;
	}

	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
		interface = fm_info_get_enet_if(i);
		switch (interface) {
		case PHY_INTERFACE_MODE_RGMII:
		case PHY_INTERFACE_MODE_RGMII_TXID:
		case PHY_INTERFACE_MODE_RGMII_RXID:
		case PHY_INTERFACE_MODE_RGMII_ID:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		case PHY_INTERFACE_MODE_SGMII:
#if defined(CONFIG_TARGET_T1023RDB)
			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
#elif defined(CONFIG_TARGET_T1024RDB)
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
#endif
			fm_info_set_mdio(i, dev);
			break;
		case PHY_INTERFACE_MODE_2500BASEX:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
		switch (fm_info_get_enet_if(i)) {
		case PHY_INTERFACE_MODE_XGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

	cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */

	return pci_eth_init(bis);
}

void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
			      enum fm_port port, int offset)
{
#if defined(CONFIG_TARGET_T1024RDB)
	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
			(port == FM1_DTSEC3)) {
		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
		fdt_setprop_string(fdt, offset, "phy-connection-type",
				   "2500base-x");
		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
	}
#endif
}

void fdt_fixup_board_enet(void *fdt)
{
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
48c6f328 SL	2	/*
	3	* Copyright 2014 Freescale Semiconductor, Inc.
	4	*
e8a7f1c3	5	* Shengzhou Liu <Shengzhou.Liu@freescale.com>
48c6f328 SL	6	*/
48c6f328 SL	7
d678a59d	8	#include <common.h>
48c6f328	9	#include <command.h>
4d72caa5	10	#include <fdt_support.h>
90526e9f	11	#include <net.h>
48c6f328 SL	12	#include <netdev.h>
	13	#include <asm/mmu.h>
	14	#include <asm/processor.h>
	15	#include <asm/immap_85xx.h>
	16	#include <asm/fsl_law.h>
	17	#include <asm/fsl_serdes.h>
	18	#include <asm/fsl_portals.h>
	19	#include <asm/fsl_liodn.h>
	20	#include <malloc.h>
	21	#include <fm_eth.h>
	22	#include <fsl_mdio.h>
	23	#include <miiphy.h>
	24	#include <phy.h>
8225b2fd	25	#include <fsl_dtsec.h>
48c6f328	26	#include <asm/fsl_serdes.h>
e26416a3	27	#include "../common/fman.h"
48c6f328	28
b75d8dc5	29	int board_eth_init(struct bd_info *bis)
48c6f328 SL	30	{
	31	#if defined(CONFIG_FMAN_ENET)
	32	int i, interface;
	33	struct memac_mdio_info dtsec_mdio_info;
	34	struct memac_mdio_info tgec_mdio_info;
	35	struct mii_dev *dev;
5155207a	36	ccsr_gur_t gur = (void )(CFG_SYS_MPC85xx_GUTS_ADDR);
48c6f328 SL	37	u32 srds_s1;
	38
	39	srds_s1 = in_be32(&gur->rcwsr[4]) &
	40	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	41	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
	42
	43	dtsec_mdio_info.regs =
6e7df1d1	44	(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
48c6f328 SL	45
	46	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
	47
	48	/* Register the 1G MDIO bus */
	49	fm_memac_mdio_init(bis, &dtsec_mdio_info);
	50
	51	tgec_mdio_info.regs =
6e7df1d1	52	(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
48c6f328 SL	53	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
	54
	55	/* Register the 10G MDIO bus */
	56	fm_memac_mdio_init(bis, &tgec_mdio_info);
	57
e26416a3	58	/* Set the on-board RGMII PHY address */
48c6f328 SL	59	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
	60
	61	switch (srds_s1) {
960286b6	62	#ifdef CONFIG_TARGET_T1024RDB
48c6f328	63	case 0x95:
e26416a3 SL	64	/* set the on-board RGMII2 PHY */
	65	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
	66
77b11f76	67	/* set 10GBase-R with Aquantia AQR105 PHY */
48c6f328 SL	68	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
48c6f328 SL	69	break;
e8a7f1c3 SL	70	#endif
	71	case 0x6a:
	72	case 0x6b:
e26416a3 SL	73	case 0x77:
	74	case 0x135:
	75	/* set the on-board 2.5G SGMII AQR105 PHY */
e8a7f1c3	76	fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
9082405d	77	#ifdef CONFIG_TARGET_T1023RDB
e8a7f1c3 SL	78	/* set the on-board 1G SGMII RTL8211F PHY */
	79	fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
	80	#endif
e26416a3	81	break;
48c6f328 SL	82	default:
	83	printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
	84	srds_s1);
	85	break;
	86	}
	87
cdc5ed8f	88	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
48c6f328 SL	89	interface = fm_info_get_enet_if(i);
	90	switch (interface) {
	91	case PHY_INTERFACE_MODE_RGMII:
848a2efd MB	92	case PHY_INTERFACE_MODE_RGMII_TXID:
	93	case PHY_INTERFACE_MODE_RGMII_RXID:
	94	case PHY_INTERFACE_MODE_RGMII_ID:
48c6f328 SL	95	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	96	fm_info_set_mdio(i, dev);
	97	break;
e8a7f1c3	98	case PHY_INTERFACE_MODE_SGMII:
9082405d	99	#if defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3	100	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
960286b6	101	#elif defined(CONFIG_TARGET_T1024RDB)
e8a7f1c3 SL	102	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	103	#endif
	104	fm_info_set_mdio(i, dev);
	105	break;
7c2d5d16	106	case PHY_INTERFACE_MODE_2500BASEX:
e26416a3 SL	107	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	108	fm_info_set_mdio(i, dev);
	109	break;
48c6f328 SL	110	default:
	111	break;
	112	}
	113	}
	114
cdc5ed8f	115	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
48c6f328 SL	116	switch (fm_info_get_enet_if(i)) {
	117	case PHY_INTERFACE_MODE_XGMII:
	118	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	119	fm_info_set_mdio(i, dev);
	120	break;
	121	default:
	122	break;
	123	}
	124	}
	125
	126	cpu_eth_init(bis);
	127	#endif /* CONFIG_FMAN_ENET */
	128
	129	return pci_eth_init(bis);
	130	}
	131
e26416a3 SL	132	void board_ft_fman_fixup_port(void fdt, char compat, phys_addr_t addr,
	133	enum fm_port port, int offset)
	134	{
960286b6	135	#if defined(CONFIG_TARGET_T1024RDB)
7c2d5d16	136	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) \|\|
e8a7f1c3 SL	137	(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
e8a7f1c3 SL	138	(port == FM1_DTSEC3)) {
e26416a3	139	fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
ea753267	140	fdt_setprop_string(fdt, offset, "phy-connection-type",
7c2d5d16	141	"2500base-x");
e26416a3 SL	142	fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
e26416a3 SL	143	}
e8a7f1c3	144	#endif
e26416a3 SL	145	}
e26416a3 SL	146
48c6f328 SL	147	void fdt_fixup_board_enet(void *fdt)
	148	{
	149	}